project.vim
build/
stage1.tar.xz
+musl-cross-make/stage1
+musl-cross-make/stage2
+musl-cross-make/sources/
--- /dev/null
+
+OUTPUT = $(PWD)/output
+SOURCES = sources
+
+CONFIG_SUB_REV = 3d5db9ebe860
+BINUTILS_VER = 2.25.1
+GCC_VER = 5.3.0
+MUSL_VER = 1.1.15
+GMP_VER = 6.1.1
+MPC_VER = 1.0.3
+MPFR_VER = 3.1.4
+LINUX_VER = 4.4.10
+
+GNU_SITE = https://ftp.gnu.org/pub/gnu
+GCC_SITE = $(GNU_SITE)/gcc
+BINUTILS_SITE = $(GNU_SITE)/binutils
+GMP_SITE = $(GNU_SITE)/gmp
+MPC_SITE = $(GNU_SITE)/mpc
+MPFR_SITE = $(GNU_SITE)/mpfr
+ISL_SITE = http://isl.gforge.inria.fr/
+
+MUSL_SITE = https://www.musl-libc.org/releases
+MUSL_REPO = git://git.musl-libc.org/musl
+
+LINUX_SITE = https://cdn.kernel.org/pub/linux/kernel
+
+BUILD_DIR = build-$(TARGET)
+
+-include config.mak
+
+SRC_DIRS = gcc-$(GCC_VER) binutils-$(BINUTILS_VER) musl-$(MUSL_VER) \
+ $(if $(GMP_VER),gmp-$(GMP_VER)) \
+ $(if $(MPC_VER),mpc-$(MPC_VER)) \
+ $(if $(MPFR_VER),mpfr-$(MPFR_VER)) \
+ $(if $(ISL_VER),isl-$(ISL_VER)) \
+ $(if $(LINUX_VER),linux-$(LINUX_VER))
+
+all:
+
+clean:
+ rm -rf gcc-* binutils-* musl-* gmp-* mpc-* mpfr-* isl-* build-* linux-*
+
+distclean: clean
+ rm -rf sources
+
+
+# Rules for downloading and verifying sources. Treat an external SOURCES path as
+# immutable and do not try to download anything into it.
+
+ifeq ($(SOURCES),sources)
+
+$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/gmp*)): SITE = $(GMP_SITE)
+$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/mpc*)): SITE = $(MPC_SITE)
+$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/mpfr*)): SITE = $(MPFR_SITE)
+$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/isl*)): SITE = $(ISL_SITE)
+$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/binutils*)): SITE = $(BINUTILS_SITE)
+$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/gcc*)): SITE = $(GCC_SITE)/$(basename $(basename $(notdir $@)))
+$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/musl*)): SITE = $(MUSL_SITE)
+$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/linux-4*)): SITE = $(LINUX_SITE)/v4.x
+$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/linux-3*)): SITE = $(LINUX_SITE)/v3.x
+$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/linux-2.6*)): SITE = $(LINUX_SITE)/v2.6
+
+$(SOURCES):
+ mkdir -p $@
+
+$(SOURCES)/config.sub: | $(SOURCES)
+ mkdir -p $@.tmp
+ cd $@.tmp && wget -c -O $(notdir $@) "http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.sub;hb=$(CONFIG_SUB_REV)"
+ cd $@.tmp && touch $(notdir $@)
+ cd $@.tmp && sha1sum -c $(PWD)/hashes/$(notdir $@).$(CONFIG_SUB_REV).sha1
+ mv $@.tmp/$(notdir $@) $@
+ rm -rf $@.tmp
+
+$(SOURCES)/%: hashes/%.sha1 | $(SOURCES)
+ mkdir -p $@.tmp
+ cd $@.tmp && wget -c -O $(notdir $@) $(SITE)/$(notdir $@)
+ cd $@.tmp && touch $(notdir $@)
+ cd $@.tmp && sha1sum -c $(PWD)/hashes/$(notdir $@).sha1
+ mv $@.tmp/$(notdir $@) $@
+ rm -rf $@.tmp
+
+endif
+
+
+# Rules for extracting and patching sources, or checking them out from git.
+
+musl-git-%:
+ rm -rf $@.tmp
+ git clone -b $(patsubst musl-git-%,%,$@) $(MUSL_REPO) $@.tmp
+ cd $@.tmp && git fsck
+ mv $@.tmp $@
+
+%: $(SOURCES)/%.tar.gz | $(SOURCES)/config.sub
+ rm -rf $@.tmp
+ mkdir $@.tmp
+ ( cd $@.tmp && tar zxvf - ) < $<
+ test ! -d patches/$@ || cat patches/$@/* | ( cd $@.tmp/$@ && patch -p1 )
+ test ! -f $@.tmp/$@/config.sub || cp -f $(SOURCES)/config.sub $@.tmp/$@
+ rm -rf $@
+ touch $@.tmp/$@
+ mv $@.tmp/$@ $@
+ rm -rf $@.tmp
+
+%: $(SOURCES)/%.tar.bz2 | $(SOURCES)/config.sub
+ rm -rf $@.tmp
+ mkdir $@.tmp
+ ( cd $@.tmp && tar jxvf - ) < $<
+ test ! -d patches/$@ || cat patches/$@/* | ( cd $@.tmp/$@ && patch -p1 )
+ test ! -f $@.tmp/$@/config.sub || cp -f $(SOURCES)/config.sub $@.tmp/$@
+ rm -rf $@
+ touch $@.tmp/$@
+ mv $@.tmp/$@ $@
+ rm -rf $@.tmp
+
+%: $(SOURCES)/%.tar.xz | $(SOURCES)/config.sub
+ rm -rf $@.tmp
+ mkdir $@.tmp
+ ( cd $@.tmp && tar Jxvf - ) < $<
+ test ! -d patches/$@ || cat patches/$@/* | ( cd $@.tmp/$@ && patch -p1 )
+ test ! -f $@.tmp/$@/config.sub || cp -f $(SOURCES)/config.sub $@.tmp/$@
+ rm -rf $@
+ touch $@.tmp/$@
+ mv $@.tmp/$@ $@
+ rm -rf $@.tmp
+
+extract_all: | $(SRC_DIRS)
+
+
+# Rules for building.
+
+ifeq ($(TARGET),)
+
+all:
+ @echo TARGET must be set via config.mak or command line.
+ @exit 1
+
+else
+
+$(BUILD_DIR):
+ mkdir -p $@
+
+$(BUILD_DIR)/Makefile: | $(BUILD_DIR)
+ ln -sf ../litecross/Makefile $@
+
+$(BUILD_DIR)/config.mak: | $(BUILD_DIR)
+ printf >$@ -- '%s\n' \
+ "MUSL_SRCDIR = ../musl-$(MUSL_VER)" \
+ "GCC_SRCDIR = ../gcc-$(GCC_VER)" \
+ "BINUTILS_SRCDIR = ../binutils-$(BINUTILS_VER)" \
+ $(if $(GMP_VER),"GMP_SRCDIR = ../gmp-$(GMP_VER)") \
+ $(if $(MPC_VER),"MPC_SRCDIR = ../mpc-$(MPC_VER)") \
+ $(if $(MPFR_VER),"MPFR_SRCDIR = ../mpfr-$(MPFR_VER)") \
+ $(if $(ISL_VER),"ISL_SRCDIR = ../isl-$(ISL_VER)") \
+ $(if $(LINUX_VER),"LINUX_SRCDIR = ../linux-$(LINUX_VER)") \
+ "-include ../config.mak"
+
+all: | $(SRC_DIRS) $(BUILD_DIR) $(BUILD_DIR)/Makefile $(BUILD_DIR)/config.mak
+ cd $(BUILD_DIR) && $(MAKE) $@
+
+install: | $(SRC_DIRS) $(BUILD_DIR) $(BUILD_DIR)/Makefile $(BUILD_DIR)/config.mak
+ cd $(BUILD_DIR) && $(MAKE) OUTPUT=$(OUTPUT) $@
+
+endif
--- /dev/null
+musl-cross-make
+===============
+
+This is a the second generation of musl-cross-make, a fast, simple,
+but advanced makefile-based approach for producing musl-targeting
+cross compilers. Features include:
+
+- Single-stage GCC build, used to build both musl libc and its own
+ shared target libs depending on libc.
+
+- No hard-coded absoluete paths; resulting cross compilers can be
+ copied/moved anywhere.
+
+- Ability to build multiple cross compilers for different targets
+ using a single set of patched source trees.
+
+- Nothing is installed until running "make install", and the
+ installation location can be chosen at install time.
+
+- Automatic download of source packages, including GCC prerequisites
+ (GMP, MPC, MPFR), using https and checking hashes.
+
+- Automatic patching with canonical musl support patches and patches
+ which provide bug fixes and features musl depends on for some arch
+ targets.
+
+
+Usage
+-----
+
+The build system can be configured by providing a config.mak file in
+the top-level directory. The only mandatory variable is TARGET, which
+should contain a gcc target tuple (such as i486-linux-musl), but many
+more options are available. See the provided config.mak.dist and
+presets/* for examples.
+
+To compile, run make. To install to $(OUTPUT), run "make install".
+
+The default value for $(OUTPUT) is output; after installing here you
+can move the cross compiler toolchain to another location as desired.
+
+
+
+How it works
+------------
+
+The current musl-cross-make is factored into two layers:
+
+1. The top-level Makefile which is responsible for downloading,
+ verifying, extracting, and patching sources, and for setting up a
+ build directory, and
+
+2. Litecross, the cross compiler build system, which is itself a
+ Makefile symlinked into the build directory.
+
+Most of the real magic takes place in litecross. It begins by setting
+up symlinks to all the source trees provided to it by the caller, then
+builds a combined "src_toolchain" directory of symlinks that combines
+the contents of the top-level gcc and binutils source trees and
+symlinks to gmp, mpc, and mpfr. One configured invocation them
+configures all the GNU toolchain components together in a manner that
+does not require any of them to be installed in order for the others
+to use them.
+
+Rather than building the whole toolchain tree at once, though,
+litecross starts by building just the gcc directory and its
+prerequisites, to get an "xgcc" that can be used to configure musl. It
+then configures musl, installs musl's headers to a staging "build
+sysroot", and builds libgcc.a using those headers. At this point it
+has all the prerequisites to build musl libc.a and libc.so, which the
+rest of the gcc target-libs depend on; once they are built, the full
+toolchain "make all" can proceed.
+
+Litecross does not actually depend on the musl-cross-make top-level
+build system; it can be used with any pre-extracted, properly patched
+set of source trees.
+
+
+Project scope and goals
+-----------------------
+
+The primary goals of this project are to:
+
+- Provide canonical musl support patches for GCC and binutils.
+
+- Serve as a canonical example of how GCC should be built to target
+ musl.
+
+- Streamline the production of musl-targeting cross compilers so that
+ musl users can easily produce musl-linked applications or bootstrap
+ new systems using musl.
+
+- Assist musl and toolchain developers in development and testing.
+
+While the patches applied to GCC and binutils are all intended not to
+break non-musl configurations, musl-cross-make itself is specific to
+musl. Changes to add support for exotic target variants outside of
+what upstream musl supports are probably out-of-scope unless they are
+non-invasive. Changes to fix issues building musl-cross-make to run on
+non-Linux systems are well within scope as long as they are clean.
+
+Most importantly, this is a side project to benefit musl and its
+users. It's not intended to be something high-maintenance or to divert
+development effort away from musl itself.
+
+
+Patches included
+----------------
+
+In addition to canonical musl support patches for GCC,
+musl-cross-make's patch set provides:
+
+- Static-linked PIE support
+- Addition of --enable-default-pie
+- Fixes for SH-specific bugs and bitrot in GCC
+- Support for J2 Core CPU target in GCC & binutils
+- SH/FDPIC ABI support
+
+Most of these patches are integrated in gcc trunk/binutils master.
+They should also be usable with Gregor's original musl-cross or other
+build systems, if desired.
+
+Some functionality (SH/FDPIC, and support for J2 specific features) is
+presently only available with gcc 5.2.0 and binutils 2.25.1.
--- /dev/null
+#
+# config.mak.dist - sample musl-cross-make configuration
+#
+# Copy to config.mak and edit as desired.
+#
+
+# There is no default TARGET; you must select one here or on the make
+# command line. Some examples:
+
+# TARGET = i486-linux-musl
+TARGET = x86_64-linux-musl
+# TARGET = arm-linux-musleabi
+# TARGET = arm-linux-musleabihf
+# TARGET = sh2eb-linux-muslfdpic
+# ...
+
+# By default, cross compilers are installed to ./output under the top-level
+# musl-cross-make directory and can later be moved wherever you want them.
+# To install directly to a specific location, set it here. Multiple targets
+# can safely be installed in the same location. Some examples:
+
+OUTPUT = $(PWD)/stage2
+
+# By default, latest supported release versions of musl and the toolchain
+# components are used. You can override those here, but the version selected
+# must be supported (under hashes/ and patches/) to work. For musl, you
+# can use "git-refname" (e.g. git-master) instead of a release. Setting a
+# blank version for gmp, mpc, mpfr and isl will suppress download and
+# in-tree build of these libraries and instead depend on pre-installed
+# libraries when available (isl is optional and not set by default).
+# Setting a blank version for linux will suppress installation of kernel
+# headers, which are not needed unless compiling programs that use them.
+
+# BINUTILS_VER = 2.25.1
+# GCC_VER = 5.2.0
+# MUSL_VER = git-master
+# GMP_VER =
+# MPC_VER =
+# MPFR_VER =
+# ISL_VER =
+# LINUX_VER =
+
+# Something like the following can be used to produce a static-linked
+# toolchain that's deployable to any system with matching arch, using
+# an existing musl-targeted cross compiler. This only # works if the
+# system you build on can natively (or via binfmt_misc and # qemu) run
+# binaries produced by the existing toolchain (in this example, i486).
+
+COMMON_CONFIG += CC="x86_64-linux-musl-gcc -static --static" CXX="x86_64-linux-musl-g++ -static --static"
+
+# Recommended options for smaller build for deploying binaries:
+
+COMMON_CONFIG += CFLAGS="-g0 -Os" CXXFLAGS="-g0 -Os" LDFLAGS="-s"
+
+# Recommended options for faster/simpler build:
+
+COMMON_CONFIG += --disable-nls
+GCC_CONFIG += --enable-languages=c,c++
+GCC_CONFIG += --disable-libquadmath --disable-decimal-float
+GCC_CONFIG += --disable-multilib
+
+# You can keep the local build path out of your toolchain binaries and
+# target libraries with the following, but then gdb needs to be told
+# where to look for source files.
+
+# COMMON_CONFIG += --with-debug-prefix-map=$(PWD)=
--- /dev/null
+#
+# config.mak.dist - sample musl-cross-make configuration
+#
+# Copy to config.mak and edit as desired.
+#
+
+# There is no default TARGET; you must select one here or on the make
+# command line. Some examples:
+
+# TARGET = i486-linux-musl
+# TARGET = x86_64-linux-musl
+# TARGET = arm-linux-musleabi
+# TARGET = arm-linux-musleabihf
+# TARGET = sh2eb-linux-muslfdpic
+# ...
+
+# By default, cross compilers are installed to ./output under the top-level
+# musl-cross-make directory and can later be moved wherever you want them.
+# To install directly to a specific location, set it here. Multiple targets
+# can safely be installed in the same location. Some examples:
+
+# OUTPUT = /opt/cross
+# OUTPUT = /usr/local
+
+# By default, latest supported release versions of musl and the toolchain
+# components are used. You can override those here, but the version selected
+# must be supported (under hashes/ and patches/) to work. For musl, you
+# can use "git-refname" (e.g. git-master) instead of a release. Setting a
+# blank version for gmp, mpc, mpfr and isl will suppress download and
+# in-tree build of these libraries and instead depend on pre-installed
+# libraries when available (isl is optional and not set by default).
+# Setting a blank version for linux will suppress installation of kernel
+# headers, which are not needed unless compiling programs that use them.
+
+# BINUTILS_VER = 2.25.1
+# GCC_VER = 5.2.0
+# MUSL_VER = git-master
+# GMP_VER =
+# MPC_VER =
+# MPFR_VER =
+# ISL_VER =
+# LINUX_VER =
+
+# Something like the following can be used to produce a static-linked
+# toolchain that's deployable to any system with matching arch, using
+# an existing musl-targeted cross compiler. This only # works if the
+# system you build on can natively (or via binfmt_misc and # qemu) run
+# binaries produced by the existing toolchain (in this example, i486).
+
+# COMMON_CONFIG += CC="i486-linux-musl-gcc -static --static" CXX="i486-linux-musl-g++ -static --static"
+
+# Recommended options for smaller build for deploying binaries:
+
+# COMMON_CONFIG += CFLAGS="-g0 -Os" CXXFLAGS="-g0 -Os" LDFLAGS="-s"
+
+# Recommended options for faster/simpler build:
+
+# COMMON_CONFIG += --disable-nls
+# GCC_CONFIG += --enable-languages=c,c++
+# GCC_CONFIG += --disable-libquadmath --disable-decimal-float
+# GCC_CONFIG += --disable-multilib
+
+# You can keep the local build path out of your toolchain binaries and
+# target libraries with the following, but then gdb needs to be told
+# where to look for source files.
+
+# COMMON_CONFIG += --with-debug-prefix-map=$(PWD)=
--- /dev/null
+1d597ae063e3947a5f61e23ceda8aebf78405fcd binutils-2.25.1.tar.bz2
--- /dev/null
+f74f1ce2e62c516ba832f99a94289930be7869cf binutils-397a64b3.tar.bz2
--- /dev/null
+7d66e32bb3cce017e1cc9bef59fb6f8271fb7fec config.sub
--- /dev/null
+b8a55b13c4e38fae78d5db9a456e2d4ffe003118 gcc-4.2.1.tar.bz2
--- /dev/null
+f3359a157b3536f289c155363f1736a2c9b414db gcc-4.7.4.tar.bz2
--- /dev/null
+fe3f5390949d47054b613edc36c557eb1d51c18e gcc-5.2.0.tar.bz2
--- /dev/null
+0612270b103941da08376df4d0ef4e5662a2e9eb gcc-5.3.0.tar.bz2
--- /dev/null
+db38c7b67f8eea9f2e5b8a48d219165b2fdab11f gmp-6.1.0.tar.bz2
--- /dev/null
+757d672e66d8e0afe60ca04735ab11c00d9346e4 gmp-6.1.1.tar.bz2
--- /dev/null
+b653327b20e807d1df3a7e2f546ea924f1e030c0 isl-0.14.1.tar.bz2
--- /dev/null
+1e30e09a5fc2c9e1aa4bdb8c9c21fdff20a7cd12 isl-0.15.tar.bz2
--- /dev/null
+4fc189bd50b734c08985c61bd16cc91cd3fc4e04 linux-2.6.35.tar.xz
--- /dev/null
+03b45399a93ae8bc18f1f27ad72f3e98c6bba5c8 linux-4.4.10.tar.xz
--- /dev/null
+b8be66396c726fdc36ebb0f692ed8a8cca3bcc66 mpc-1.0.3.tar.gz
--- /dev/null
+e3b0af77f18505184410d621fe0aae179e229dba mpfr-3.1.4.tar.bz2
--- /dev/null
+b71208e87e66ac959d0e413dd444279d28a7bff1 musl-1.1.14.tar.gz
--- /dev/null
+027c3ae2182fa53c2b554ca98a28dc5cfca4b2c3 musl-1.1.15.tar.gz
--- /dev/null
+
+OUTPUT = $(PWD)/output
+
+BINUTILS_SRCDIR = BINUTILS_SRCDIR_not_set
+GCC_SRCDIR = GCC_SRCDIR_not_set
+MUSL_SRCDIR = MUSL_SRCDIR_not_set
+
+GCC_CONFIG_FOR_TARGET =
+COMMON_CONFIG =
+GCC_CONFIG =
+TOOLCHAIN_CONFIG =
+
+XGCC_DIR = ../obj_toolchain/gcc
+XGCC = $(XGCC_DIR)/xgcc -B $(XGCC_DIR)
+
+-include config.mak
+
+ifneq ($(findstring fdpic,$(TARGET)),)
+GCC_CONFIG_FOR_TARGET += --enable-fdpic
+endif
+
+ifneq ($(filter x86_64%x32,$(TARGET)),)
+GCC_CONFIG_FOR_TARGET += --with-abi=x32
+endif
+
+ifneq ($(findstring mips64,$(TARGET))$(findstring mipsisa64,$(TARGET)),)
+ifneq ($(findstring n32,$(TARGET)),)
+GCC_CONFIG_FOR_TARGET += --with-abi=n32
+else
+GCC_CONFIG_FOR_TARGET += --with-abi=64
+endif
+endif
+
+ifneq ($(filter %sf,$(TARGET)),)
+GCC_CONFIG_FOR_TARGET += --with-float=soft
+endif
+
+ifneq ($(filter %hf,$(TARGET)),)
+GCC_CONFIG_FOR_TARGET += --with-float=hard
+endif
+
+
+MAKE += MULTILIB_OSDIRNAMES=
+MAKE += INFO_DEPS= infodir=
+MAKE += ac_cv_prog_lex_root=lex.yy.c
+
+FULL_TOOLCHAIN_CONFIG = --enable-languages=c,c++ \
+ $(GCC_CONFIG_FOR_TARGET) \
+ $(COMMON_CONFIG) $(GCC_CONFIG) $(TOOLCHAIN_CONFIG) \
+ --disable-werror \
+ --target=$(TARGET) --prefix= \
+ --libdir=/lib --disable-multilib \
+ --with-sysroot=$(SYSROOT) \
+ --with-build-sysroot='$$(LC_ROOT)/obj_sysroot' \
+ --enable-tls \
+ --disable-libmudflap --disable-libsanitizer \
+ --disable-gnu-indirect-function \
+ --disable-libmpx \
+ --enable-libstdcxx-time
+
+FULL_MUSL_CONFIG = $(MUSL_CONFIG) \
+ --prefix= --host=$(TARGET)
+
+ifeq ($(NATIVE),)
+SYSROOT = /$(TARGET)
+FULL_MUSL_CONFIG += CC="$(XGCC)" LIBCC="../obj_toolchain/$(TARGET)/libgcc/libgcc.a"
+MUSL_VARS = AR=../obj_toolchain/binutils/ar RANLIB=../obj_toolchain/binutils/ranlib
+obj_musl/.lc_built: | obj_toolchain/$(TARGET)/libgcc/libgcc.a
+obj_toolchain/.lc_built: | obj_sysroot/.lc_libs obj_sysroot/.lc_headers
+else
+SYSROOT = /
+FULL_TOOLCHAIN_CONFIG += --host=$(TARGET)
+MUSL_VARS =
+endif
+
+ifeq ($(TARGET),)
+
+all:
+ @echo TARGET must be set.
+ @exit 1
+
+install: all
+
+else
+
+all: musl toolchain
+
+install: install-musl install-toolchain
+
+musl: obj_musl/.lc_built
+
+toolchain: obj_toolchain/.lc_built
+
+.PHONY: all musl toolchain install-musl install-toolchain clean
+
+src_binutils: | $(BINUTILS_SRCDIR)
+ ln -sf $(BINUTILS_SRCDIR) $@
+
+src_gcc: | $(GCC_SRCDIR)
+ ln -sf $(GCC_SRCDIR) $@
+
+src_musl: | $(MUSL_SRCDIR)
+ ln -sf $(MUSL_SRCDIR) $@
+
+ifneq ($(GMP_SRCDIR),)
+src_toolchain: src_gmp
+src_gmp: | $(GMP_SRCDIR)
+ ln -sf "$(GMP_SRCDIR)" $@
+endif
+
+ifneq ($(MPC_SRCDIR),)
+src_toolchain: src_mpc
+src_mpc: | $(MPC_SRCDIR)
+ ln -sf "$(MPC_SRCDIR)" $@
+endif
+
+ifneq ($(MPFR_SRCDIR),)
+src_toolchain: src_mpfr
+src_mpfr: | $(MPFR_SRCDIR)
+ ln -sf "$(MPFR_SRCDIR)" $@
+endif
+
+ifneq ($(ISL_SRCDIR),)
+src_toolchain: src_isl
+src_isl: | $(ISL_SRCDIR)
+ ln -sf "$(ISL_SRCDIR)" $@
+endif
+
+src_toolchain: src_binutils src_gcc
+ rm -rf $@ $@.tmp
+ mkdir $@.tmp
+ cd $@.tmp && ln -sf ../src_binutils/* .
+ cd $@.tmp && ln -sf ../src_gcc/* .
+ $(if $(GMP_SRCDIR),cd $@.tmp && ln -sf ../src_gmp gmp)
+ $(if $(MPC_SRCDIR),cd $@.tmp && ln -sf ../src_mpc mpc)
+ $(if $(MPFR_SRCDIR),cd $@.tmp && ln -sf ../src_mpfr mpfr)
+ $(if $(ISL_SRCDIR),cd $@.tmp && ln -sf ../src_isl isl)
+ mv $@.tmp $@
+
+obj_%:
+ mkdir -p $@
+
+obj_sysroot/include:
+ mkdir -p $@
+
+obj_sysroot/usr: | obj_sysroot
+ ln -sf . $@
+
+obj_sysroot/lib64: | obj_sysroot
+ ln -sf lib $@
+
+obj_toolchain/.lc_configured: | obj_toolchain src_toolchain
+ cd obj_toolchain && ../src_toolchain/configure $(FULL_TOOLCHAIN_CONFIG)
+ touch $@
+
+obj_toolchain/gcc/.lc_built: | obj_toolchain/.lc_configured obj_sysroot/usr obj_sysroot/lib64 obj_sysroot/include
+ cd obj_toolchain && $(MAKE) MAKE="$(MAKE)" LC_ROOT=$(PWD) all-gcc
+ touch $@
+
+obj_musl/.lc_configured: | obj_toolchain/gcc/.lc_built obj_musl src_musl
+ cd obj_musl && ../src_musl/configure $(FULL_MUSL_CONFIG)
+ touch $@
+
+obj_sysroot/.lc_headers: | obj_musl/.lc_configured obj_sysroot
+ cd obj_musl && $(MAKE) DESTDIR=$(PWD)/obj_sysroot install-headers
+ touch $@
+
+obj_toolchain/$(TARGET)/libgcc/.lc_configured: | obj_sysroot/.lc_headers
+ cd obj_toolchain && $(MAKE) MAKE="$(MAKE)" LC_ROOT=$(PWD) configure-target-libgcc
+ touch $@
+
+obj_toolchain/$(TARGET)/libgcc/libgcc.a: | obj_toolchain/$(TARGET)/libgcc/.lc_configured
+ cd $(dir $@) && $(MAKE) MAKE="$(MAKE)" LC_ROOT=$(PWD) libgcc.a
+
+obj_musl/.lc_built: | obj_musl/.lc_configured
+ cd obj_musl && $(MAKE) $(MUSL_VARS)
+ touch $@
+
+obj_sysroot/.lc_libs: | obj_musl/.lc_built
+ cd obj_musl && $(MAKE) $(MUSL_VARS) DESTDIR=$(PWD)/obj_sysroot install
+ touch $@
+
+obj_toolchain/.lc_built: | obj_toolchain/.lc_configured obj_toolchain/gcc/.lc_built
+ cd obj_toolchain && $(MAKE) MAKE="$(MAKE)" LC_ROOT=$(PWD)
+ touch $@
+
+install-musl: | obj_musl/.lc_built
+ cd obj_musl && $(MAKE) $(MUSL_VARS) DESTDIR=$(DESTDIR)$(OUTPUT)$(SYSROOT) install
+
+install-toolchain: | obj_toolchain/.lc_built
+ cd obj_toolchain && $(MAKE) MAKE="$(MAKE)" LC_ROOT=$(PWD) DESTDIR=$(DESTDIR)$(OUTPUT) install
+ ln -sf $(TARGET)-gcc $(DESTDIR)$(OUTPUT)/bin/$(TARGET)-cc
+
+ifneq ($(LINUX_SRCDIR),)
+TARGET_ARCH = $(firstword $(subst -, ,$(TARGET)))
+TARGET_ARCH_MANGLED = $(patsubst i%86,x86,$(patsubst aarch64%,arm64%,$(TARGET_ARCH)))
+LINUX_ARCH_LIST = $(sort $(notdir $(wildcard $(LINUX_SRCDIR)/arch/*)))
+LINUX_ARCH = $(firstword $(foreach a,$(LINUX_ARCH_LIST),$(findstring $(a),$(TARGET_ARCH_MANGLED))))
+ifneq ($(LINUX_ARCH),)
+all: kernel-headers
+install: install-kernel-headers
+kernel-headers: | obj_kernel_headers/.lc_built
+src_kernel_headers: | $(LINUX_SRCDIR)
+ ln -sf "$(LINUX_SRCDIR)" $@
+obj_kernel_headers/.lc_built: | src_kernel_headers
+ mkdir -p $(PWD)/obj_kernel_headers/staged
+ cd src_kernel_headers && $(MAKE) ARCH=$(LINUX_ARCH) O=$(PWD)/obj_kernel_headers INSTALL_HDR_PATH=$(PWD)/obj_kernel_headers/staged headers_install
+ touch $@
+install-kernel-headers: | obj_kernel_headers/.lc_built
+ mkdir -p $(DESTDIR)$(OUTPUT)$(SYSROOT)/include
+ cp -R obj_kernel_headers/staged/include/* $(DESTDIR)$(OUTPUT)$(SYSROOT)/include
+endif
+endif
+
+endif
+
+clean:
+ rm -rf src_* obj_*
--- /dev/null
+diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
+index bd4b576..41803c2 100644
+--- a/bfd/elf32-arm.c
++++ b/bfd/elf32-arm.c
+@@ -13786,7 +13786,7 @@ elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+diff --git a/bfd/elf32-bfin.c b/bfd/elf32-bfin.c
+index 49ef360..8346d57 100644
+--- a/bfd/elf32-bfin.c
++++ b/bfd/elf32-bfin.c
+@@ -4257,7 +4257,7 @@ elf32_bfinfdpic_size_dynamic_sections (bfd *output_bfd,
+ if (htab->dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+diff --git a/bfd/elf32-cr16.c b/bfd/elf32-cr16.c
+index 5d8ffbc..497630e 100644
+--- a/bfd/elf32-cr16.c
++++ b/bfd/elf32-cr16.c
+@@ -2464,7 +2464,7 @@ _bfd_cr16_elf_size_dynamic_sections (bfd * output_bfd,
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ #if 0
+ s = bfd_get_linker_section (dynobj, ".interp");
+diff --git a/bfd/elf32-cris.c b/bfd/elf32-cris.c
+index 3031173..5b40524 100644
+--- a/bfd/elf32-cris.c
++++ b/bfd/elf32-cris.c
+@@ -3764,7 +3764,7 @@ elf_cris_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+diff --git a/bfd/elf32-frv.c b/bfd/elf32-frv.c
+index b55a7ab..ef72c23 100644
+--- a/bfd/elf32-frv.c
++++ b/bfd/elf32-frv.c
+@@ -5444,7 +5444,7 @@ elf32_frvfdpic_size_dynamic_sections (bfd *output_bfd,
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+diff --git a/bfd/elf32-hppa.c b/bfd/elf32-hppa.c
+index 41bf5c5..62c7cf6 100644
+--- a/bfd/elf32-hppa.c
++++ b/bfd/elf32-hppa.c
+@@ -2215,7 +2215,7 @@ elf32_hppa_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
+ if (htab->etab.dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ sec = bfd_get_linker_section (dynobj, ".interp");
+ if (sec == NULL)
+diff --git a/bfd/elf32-i370.c b/bfd/elf32-i370.c
+index 7fba4d1..458f694 100644
+--- a/bfd/elf32-i370.c
++++ b/bfd/elf32-i370.c
+@@ -594,7 +594,7 @@ i370_elf_size_dynamic_sections (bfd *output_bfd,
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+diff --git a/bfd/elf32-i386.c b/bfd/elf32-i386.c
+index 7642d0f..b0844c8 100644
+--- a/bfd/elf32-i386.c
++++ b/bfd/elf32-i386.c
+@@ -2834,7 +2834,7 @@ elf_i386_size_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info)
+ if (htab->elf.dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ if (s == NULL)
+diff --git a/bfd/elf32-lm32.c b/bfd/elf32-lm32.c
+index 23f6e5e..0805e3c 100644
+--- a/bfd/elf32-lm32.c
++++ b/bfd/elf32-lm32.c
+@@ -2141,7 +2141,7 @@ lm32_elf_size_dynamic_sections (bfd *output_bfd,
+ if (htab->root.dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+diff --git a/bfd/elf32-m32r.c b/bfd/elf32-m32r.c
+index 155d079..a2e3c7c 100644
+--- a/bfd/elf32-m32r.c
++++ b/bfd/elf32-m32r.c
+@@ -2170,7 +2170,7 @@ m32r_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
+ if (htab->root.dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+diff --git a/bfd/elf32-m68k.c b/bfd/elf32-m68k.c
+index 10d2fcb..489f3f1 100644
+--- a/bfd/elf32-m68k.c
++++ b/bfd/elf32-m68k.c
+@@ -3257,7 +3257,7 @@ elf_m68k_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+diff --git a/bfd/elf32-metag.c b/bfd/elf32-metag.c
+index 9c54a71..755c431 100644
+--- a/bfd/elf32-metag.c
++++ b/bfd/elf32-metag.c
+@@ -2848,7 +2848,7 @@ elf_metag_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
+ if (htab->etab.dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ if (s == NULL)
+diff --git a/bfd/elf32-nios2.c b/bfd/elf32-nios2.c
+index fd70007..2a2b3a6 100644
+--- a/bfd/elf32-nios2.c
++++ b/bfd/elf32-nios2.c
+@@ -5849,7 +5849,7 @@ nios2_elf32_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+diff --git a/bfd/elf32-or1k.c b/bfd/elf32-or1k.c
+index d4f92b7..a1eba09 100644
+--- a/bfd/elf32-or1k.c
++++ b/bfd/elf32-or1k.c
+@@ -2447,7 +2447,7 @@ or1k_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
+ if (htab->root.dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_section_by_name (dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+diff --git a/bfd/elf32-ppc.c b/bfd/elf32-ppc.c
+index 8415f1e..5597051 100644
+--- a/bfd/elf32-ppc.c
++++ b/bfd/elf32-ppc.c
+@@ -6191,7 +6191,7 @@ ppc_elf_size_dynamic_sections (bfd *output_bfd,
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (htab->elf.dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+diff --git a/bfd/elf32-s390.c b/bfd/elf32-s390.c
+index de37ca4..a1e628c 100644
+--- a/bfd/elf32-s390.c
++++ b/bfd/elf32-s390.c
+@@ -2039,7 +2039,7 @@ elf_s390_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
+ if (htab->elf.dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ if (s == NULL)
+diff --git a/bfd/elf32-sh.c b/bfd/elf32-sh.c
+index 012ee4e..a51453f 100644
+--- a/bfd/elf32-sh.c
++++ b/bfd/elf32-sh.c
+@@ -3349,7 +3349,7 @@ sh_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
+ if (htab->root.dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+diff --git a/bfd/elf32-tic6x.c b/bfd/elf32-tic6x.c
+index b6640ea..380ab8d 100644
+--- a/bfd/elf32-tic6x.c
++++ b/bfd/elf32-tic6x.c
+@@ -3300,7 +3300,7 @@ elf32_tic6x_size_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info)
+ if (htab->elf.dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ if (s == NULL)
+diff --git a/bfd/elf32-tilepro.c b/bfd/elf32-tilepro.c
+index cb3f896..d55be2d 100644
+--- a/bfd/elf32-tilepro.c
++++ b/bfd/elf32-tilepro.c
+@@ -2463,7 +2463,7 @@ tilepro_elf_size_dynamic_sections (bfd *output_bfd,
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+diff --git a/bfd/elf32-vax.c b/bfd/elf32-vax.c
+index 6089e8c..893ea8d 100644
+--- a/bfd/elf32-vax.c
++++ b/bfd/elf32-vax.c
+@@ -1124,7 +1124,7 @@ elf_vax_size_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info)
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+diff --git a/bfd/elf32-xtensa.c b/bfd/elf32-xtensa.c
+index 73538cd..37ea5da 100644
+--- a/bfd/elf32-xtensa.c
++++ b/bfd/elf32-xtensa.c
+@@ -1637,7 +1637,7 @@ elf_xtensa_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
+ && htab->sgotloc != NULL);
+
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ if (s == NULL)
+diff --git a/bfd/elf64-alpha.c b/bfd/elf64-alpha.c
+index f67b0af..1973cd0 100644
+--- a/bfd/elf64-alpha.c
++++ b/bfd/elf64-alpha.c
+@@ -2877,7 +2877,7 @@ elf64_alpha_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+diff --git a/bfd/elf64-hppa.c b/bfd/elf64-hppa.c
+index 6f40b88..3b628b4 100644
+--- a/bfd/elf64-hppa.c
++++ b/bfd/elf64-hppa.c
+@@ -1558,7 +1558,7 @@ elf64_hppa_size_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info)
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ sec = bfd_get_linker_section (dynobj, ".interp");
+ BFD_ASSERT (sec != NULL);
+diff --git a/bfd/elf64-ppc.c b/bfd/elf64-ppc.c
+index 8cff990..851845f 100644
+--- a/bfd/elf64-ppc.c
++++ b/bfd/elf64-ppc.c
+@@ -9748,7 +9748,7 @@ ppc64_elf_size_dynamic_sections (bfd *output_bfd,
+ if (htab->elf.dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ if (s == NULL)
+diff --git a/bfd/elf64-s390.c b/bfd/elf64-s390.c
+index 2e505f3..406bb66 100644
+--- a/bfd/elf64-s390.c
++++ b/bfd/elf64-s390.c
+@@ -1989,7 +1989,7 @@ elf_s390_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
+ if (htab->elf.dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ if (s == NULL)
+diff --git a/bfd/elf64-sh64.c b/bfd/elf64-sh64.c
+index e460895..d920598 100644
+--- a/bfd/elf64-sh64.c
++++ b/bfd/elf64-sh64.c
+@@ -3404,7 +3404,7 @@ sh64_elf64_size_dynamic_sections (bfd *output_bfd,
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+diff --git a/bfd/elf64-x86-64.c b/bfd/elf64-x86-64.c
+index f15d33e..870aadf 100644
+--- a/bfd/elf64-x86-64.c
++++ b/bfd/elf64-x86-64.c
+@@ -3181,7 +3181,7 @@ elf_x86_64_size_dynamic_sections (bfd *output_bfd,
+ if (htab->elf.dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ if (s == NULL)
+diff --git a/bfd/elflink.c b/bfd/elflink.c
+index 7f04271..5b3438d 100644
+--- a/bfd/elflink.c
++++ b/bfd/elflink.c
+@@ -246,7 +246,7 @@ _bfd_elf_link_create_dynamic_sections (bfd *abfd, struct bfd_link_info *info)
+
+ /* A dynamically linked executable has a .interp section, but a
+ shared library does not. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_make_section_anyway_with_flags (abfd, ".interp",
+ flags | SEC_READONLY);
+@@ -5763,7 +5763,7 @@ bfd_elf_size_dynamic_sections (bfd *output_bfd,
+ bfd_boolean all_defined;
+
+ *sinterpptr = bfd_get_linker_section (dynobj, ".interp");
+- BFD_ASSERT (*sinterpptr != NULL || !info->executable);
++ BFD_ASSERT (*sinterpptr != NULL || !info->executable || info->nointerp);
+
+ if (soname != NULL)
+ {
+diff --git a/bfd/elfnn-aarch64.c b/bfd/elfnn-aarch64.c
+index beedb70..599f9cf 100644
+--- a/bfd/elfnn-aarch64.c
++++ b/bfd/elfnn-aarch64.c
+@@ -7674,7 +7674,7 @@ elfNN_aarch64_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
+
+ if (htab->root.dynamic_sections_created)
+ {
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ if (s == NULL)
+diff --git a/bfd/elfnn-ia64.c b/bfd/elfnn-ia64.c
+index c45fa28..3b304d5 100644
+--- a/bfd/elfnn-ia64.c
++++ b/bfd/elfnn-ia64.c
+@@ -2992,7 +2992,7 @@ elfNN_ia64_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
+
+ /* Set the contents of the .interp section to the interpreter. */
+ if (ia64_info->root.dynamic_sections_created
+- && info->executable)
++ && info->executable && !info->nointerp)
+ {
+ sec = bfd_get_linker_section (dynobj, ".interp");
+ BFD_ASSERT (sec != NULL);
+diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
+index be1e59a..329dec3 100644
+--- a/bfd/elfxx-mips.c
++++ b/bfd/elfxx-mips.c
+@@ -9579,7 +9579,7 @@ _bfd_mips_elf_size_dynamic_sections (bfd *output_bfd,
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+diff --git a/bfd/elfxx-sparc.c b/bfd/elfxx-sparc.c
+index 9bb71a9..db0d4f1 100644
+--- a/bfd/elfxx-sparc.c
++++ b/bfd/elfxx-sparc.c
+@@ -2559,7 +2559,7 @@ _bfd_sparc_elf_size_dynamic_sections (bfd *output_bfd,
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+diff --git a/bfd/elfxx-tilegx.c b/bfd/elfxx-tilegx.c
+index 59a2f7e..6f7485a 100644
+--- a/bfd/elfxx-tilegx.c
++++ b/bfd/elfxx-tilegx.c
+@@ -2724,7 +2724,7 @@ tilegx_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+diff --git a/include/bfdlink.h b/include/bfdlink.h
+index 797a465..cf533dd 100644
+--- a/include/bfdlink.h
++++ b/include/bfdlink.h
+@@ -433,6 +433,9 @@ struct bfd_link_info
+ /* TRUE if BND prefix in PLT entries is always generated. */
+ unsigned int bndplt: 1;
+
++ /* TRUE if generation of .interp/PT_INTERP should be suppressed. */
++ unsigned int nointerp: 1;
++
+ /* Char that may appear as the first char of a symbol, but should be
+ skipped (like symbol_leading_char) when looking up symbols in
+ wrap_hash. Used by PowerPC Linux for 'dot' symbols. */
+diff --git a/ld/ld.texinfo b/ld/ld.texinfo
+index cf3b586..1e5e5cf 100644
+--- a/ld/ld.texinfo
++++ b/ld/ld.texinfo
+@@ -1426,6 +1426,13 @@ generating dynamically linked ELF executables. The default dynamic
+ linker is normally correct; don't use this unless you know what you are
+ doing.
+
++@kindex --no-dynamic-linker
++@item --no-dynamic-linker
++When producing an executable file, omit the request for a dynamic
++linker to be used at load-time. This is only meaningful for ELF
++executables that contain dynamic relocations, and usually requires
++entry point code that is capable of processing these relocations.
++
+ @kindex --fatal-warnings
+ @kindex --no-fatal-warnings
+ @item --fatal-warnings
+diff --git a/ld/ldlex.h b/ld/ldlex.h
+index 59bd14f..8b57f84 100644
+--- a/ld/ldlex.h
++++ b/ld/ldlex.h
+@@ -33,6 +33,7 @@ enum option_values
+ OPTION_DEFSYM,
+ OPTION_DEMANGLE,
+ OPTION_DYNAMIC_LINKER,
++ OPTION_NO_DYNAMIC_LINKER,
+ OPTION_SYSROOT,
+ OPTION_EB,
+ OPTION_EL,
+diff --git a/ld/lexsup.c b/ld/lexsup.c
+index 777d6e2..1b992f7 100644
+--- a/ld/lexsup.c
++++ b/ld/lexsup.c
+@@ -138,6 +138,9 @@ static const struct ld_option ld_options[] =
+ { {"dynamic-linker", required_argument, NULL, OPTION_DYNAMIC_LINKER},
+ 'I', N_("PROGRAM"), N_("Set PROGRAM as the dynamic linker to use"),
+ TWO_DASHES },
++ { {"no-dynamic-linker", no_argument, NULL, OPTION_NO_DYNAMIC_LINKER},
++ '\0', NULL, N_("Produce an executable with no program interpreter header"),
++ TWO_DASHES },
+ { {"library", required_argument, NULL, 'l'},
+ 'l', N_("LIBNAME"), N_("Search for library LIBNAME"), TWO_DASHES },
+ { {"library-path", required_argument, NULL, 'L'},
+@@ -762,6 +765,10 @@ parse_args (unsigned argc, char **argv)
+ case 'I': /* Used on Solaris. */
+ case OPTION_DYNAMIC_LINKER:
+ command_line.interpreter = optarg;
++ link_info.nointerp = 0;
++ break;
++ case OPTION_NO_DYNAMIC_LINKER:
++ link_info.nointerp = 1;
+ break;
+ case OPTION_SYSROOT:
+ /* Already handled in ldmain.c. */
--- /dev/null
+diff --git a/bfd/archures.c b/bfd/archures.c
+index 51068b9..c67d76b 100644
+--- a/bfd/archures.c
++++ b/bfd/archures.c
+@@ -294,10 +294,12 @@ DESCRIPTION
+ .#define bfd_mach_sh_dsp 0x2d
+ .#define bfd_mach_sh2a 0x2a
+ .#define bfd_mach_sh2a_nofpu 0x2b
++.#define bfd_mach_shj2 0x2c
+ .#define bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu 0x2a1
+ .#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
+ .#define bfd_mach_sh2a_or_sh4 0x2a3
+ .#define bfd_mach_sh2a_or_sh3e 0x2a4
++.#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
+ .#define bfd_mach_sh2e 0x2e
+ .#define bfd_mach_sh3 0x30
+ .#define bfd_mach_sh3_nommu 0x31
+diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
+index ca0cafd..99e92c6 100644
+--- a/bfd/bfd-in2.h
++++ b/bfd/bfd-in2.h
+@@ -2109,10 +2109,12 @@ enum bfd_architecture
+ #define bfd_mach_sh_dsp 0x2d
+ #define bfd_mach_sh2a 0x2a
+ #define bfd_mach_sh2a_nofpu 0x2b
++#define bfd_mach_shj2 0x2c
+ #define bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu 0x2a1
+ #define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
+ #define bfd_mach_sh2a_or_sh4 0x2a3
+ #define bfd_mach_sh2a_or_sh3e 0x2a4
++#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
+ #define bfd_mach_sh2e 0x2e
+ #define bfd_mach_sh3 0x30
+ #define bfd_mach_sh3_nommu 0x31
+diff --git a/bfd/cpu-sh.c b/bfd/cpu-sh.c
+index d516d66..66d21a5 100644
+--- a/bfd/cpu-sh.c
++++ b/bfd/cpu-sh.c
+@@ -44,7 +44,9 @@
+ #define SH2A_NOFPU_OR_SH3_NOMMU_NEXT arch_info_struct + 17
+ #define SH2A_OR_SH4_NEXT arch_info_struct + 18
+ #define SH2A_OR_SH3E_NEXT arch_info_struct + 19
+-#define SH64_NEXT NULL
++#define SH64_NEXT arch_info_struct + 20
++#define SHJ2_NEXT arch_info_struct + 21
++#define SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT NULL
+
+ static const bfd_arch_info_type arch_info_struct[] =
+ {
+@@ -348,6 +350,36 @@ static const bfd_arch_info_type arch_info_struct[] =
+ bfd_arch_default_fill,
+ SH64_NEXT
+ },
++ {
++ 32, /* 32 bits in a word. */
++ 32, /* 32 bits in an address. */
++ 8, /* 8 bits in a byte. */
++ bfd_arch_sh,
++ bfd_mach_shj2,
++ "sh", /* Architecture name. . */
++ "j2", /* Machine name. */
++ 1,
++ FALSE, /* Not the default. */
++ bfd_default_compatible,
++ bfd_default_scan,
++ bfd_arch_default_fill,
++ SHJ2_NEXT
++ },
++ {
++ 32, /* 32 bits in a word. */
++ 32, /* 32 bits in an address. */
++ 8, /* 8 bits in a byte. */
++ bfd_arch_sh,
++ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu,
++ "sh", /* Architecture name. . */
++ "sh2a-or-sh3e-or-j2", /* Machine name. */
++ 1,
++ FALSE, /* Not the default. */
++ bfd_default_compatible,
++ bfd_default_scan,
++ bfd_arch_default_fill,
++ SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT
++ },
+ };
+
+ const bfd_arch_info_type bfd_sh_arch =
+@@ -398,6 +430,8 @@ static struct { unsigned long bfd_mach, arch, arch_up; } bfd_to_arch_table[] =
+ { bfd_mach_sh4_nofpu, arch_sh4_nofpu, arch_sh4_nofpu_up },
+ { bfd_mach_sh4_nommu_nofpu, arch_sh4_nommu_nofpu, arch_sh4_nommu_nofpu_up },
+ { bfd_mach_sh4a_nofpu, arch_sh4a_nofpu, arch_sh4a_nofpu_up },
++ { bfd_mach_shj2, arch_shj2, arch_shj2_up },
++ { bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up },
+ { 0, 0, 0 } /* Terminator. */
+ };
+
+diff --git a/binutils/readelf.c b/binutils/readelf.c
+index a31db52..5ec21b0 100644
+--- a/binutils/readelf.c
++++ b/binutils/readelf.c
+@@ -3217,6 +3217,8 @@ get_machine_flags (unsigned e_flags, unsigned e_machine)
+ case EF_SH2A_SH3_NOFPU: strcat (buf, ", sh2a-nofpu-or-sh3-nommu"); break;
+ case EF_SH2A_SH4: strcat (buf, ", sh2a-or-sh4"); break;
+ case EF_SH2A_SH3E: strcat (buf, ", sh2a-or-sh3e"); break;
++ case EF_SHJ2: strcat (buf, ", j2"); break;
++ case EF_SH2A_SH3_SHJ2: strcat (buf, ", sh2a-nofpu-or-sh3-nommu-or-shj2 -nofpu"); break;
+ default: strcat (buf, _(", unknown ISA")); break;
+ }
+
+diff --git a/gas/config/tc-sh.c b/gas/config/tc-sh.c
+index 125f073..37f6fb0 100644
+--- a/gas/config/tc-sh.c
++++ b/gas/config/tc-sh.c
+@@ -1648,6 +1648,8 @@ get_operands (sh_opcode_info *info, char *args, sh_operand_info *operand)
+ ptr++;
+ }
+ get_operand (&ptr, operand + 2);
++ if (strcmp (info->name,"cas") == 0)
++ operand[2].type = A_IND_0;
+ }
+ else
+ {
+@@ -2187,7 +2189,10 @@ get_specific (sh_opcode_info *opcode, sh_operand_info *operands)
+ goto fail;
+ reg_m = 4;
+ break;
+-
++ case A_IND_0:
++ if (user->reg != 0)
++ goto fail;
++ break;
+ default:
+ printf (_("unhandled %d\n"), arg);
+ goto fail;
+diff --git a/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s b/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s
+index cc29889..a3e18b5 100644
+--- a/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s
++++ b/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s
+@@ -12,7 +12,5 @@
+ sh2a_nofpu_or_sh3_nommu:
+ ! Instructions introduced into sh2a-nofpu-or-sh3-nommu
+- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+
+ ! Instructions inherited from ancestors: sh sh2
+ add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+diff --git a/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s b/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
+index c702845..812aa76 100644
+--- a/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
++++ b/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
+@@ -12,7 +12,7 @@
+ sh2a_nofpu_or_sh4_nommu_nofpu:
+ ! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu
+
+-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
+ add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+ add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+ addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+@@ -119,8 +119,8 @@ sh2a_nofpu_or_sh4_nommu_nofpu:
+ rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+ rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+ sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+ shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+ shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+diff --git a/gas/testsuite/gas/sh/arch/sh2a-nofpu.s b/gas/testsuite/gas/sh/arch/sh2a-nofpu.s
+index 6f4a17e..5b38643 100644
+--- a/gas/testsuite/gas/sh/arch/sh2a-nofpu.s
++++ b/gas/testsuite/gas/sh/arch/sh2a-nofpu.s
+@@ -64,7 +64,7 @@ sh2a_nofpu:
+ movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
+ movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
+
+-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu
++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu
+ add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+ add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+ addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+@@ -171,8 +171,8 @@ sh2a_nofpu:
+ rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+ rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+ sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+ shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+ shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+diff --git a/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s b/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s
+index 25c8ae1..69d3536 100644
+--- a/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s
++++ b/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s
+@@ -13,7 +13,7 @@ sh2a_or_sh3e:
+ ! Instructions introduced into sh2a-or-sh3e
+ fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
+
+-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e
++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2e
+ add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+ add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+ addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+@@ -124,8 +124,8 @@ sh2a_or_sh3e:
+ rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+ rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+ sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+ shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+ shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+diff --git a/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s b/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s
+index d3300ca..c697268 100644
+--- a/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s
++++ b/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s
+@@ -39,7 +39,7 @@ sh2a_or_sh4:
+ fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
+ ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
+
+-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
+ add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+ add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+ addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+@@ -150,8 +150,8 @@ sh2a_or_sh4:
+ rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+ rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+ sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+ shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+ shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+diff --git a/gas/testsuite/gas/sh/arch/sh2a.s b/gas/testsuite/gas/sh/arch/sh2a.s
+index 370dbd4..0d9f3b0 100644
+--- a/gas/testsuite/gas/sh/arch/sh2a.s
++++ b/gas/testsuite/gas/sh/arch/sh2a.s
+@@ -16,7 +16,7 @@ sh2a:
+ fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32}
+ fmov.s @(2048,r5),fr1 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),<F_REG_N> */ {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32}
+
+-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
+ add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+ add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+ addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+@@ -140,8 +140,8 @@ sh2a:
+ rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+ rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+ sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+ shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+ shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+diff --git a/gas/testsuite/gas/sh/arch/sh3-dsp.s b/gas/testsuite/gas/sh/arch/sh3-dsp.s
+index acc26be..cfd4dfe 100644
+--- a/gas/testsuite/gas/sh/arch/sh3-dsp.s
++++ b/gas/testsuite/gas/sh/arch/sh3-dsp.s
+@@ -12,7 +12,7 @@
+ sh3_dsp:
+ ! Instructions introduced into sh3-dsp
+
+-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu
++! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3 sh3-nommu
+ add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+ add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+ addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+@@ -152,8 +152,8 @@ sh3_dsp:
+ setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
+ repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
+ repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
+- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+ shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+ shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+diff --git a/gas/testsuite/gas/sh/arch/sh3-nommu.s b/gas/testsuite/gas/sh/arch/sh3-nommu.s
+index 3e8ff02..dacaae1 100644
+--- a/gas/testsuite/gas/sh/arch/sh3-nommu.s
++++ b/gas/testsuite/gas/sh/arch/sh3-nommu.s
+@@ -26,7 +26,7 @@ sh3_nommu:
+ stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
+ stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
+
+-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
+ add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+ add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+ addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+@@ -133,8 +133,8 @@ sh3_nommu:
+ rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+ rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+ sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+ shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+ shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+diff --git a/gas/testsuite/gas/sh/arch/sh3.s b/gas/testsuite/gas/sh/arch/sh3.s
+index 97ab939..aa70fc3 100644
+--- a/gas/testsuite/gas/sh/arch/sh3.s
++++ b/gas/testsuite/gas/sh/arch/sh3.s
+@@ -13,7 +13,7 @@ sh3:
+ ! Instructions introduced into sh3
+ ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
+
+-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu
++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3-nommu
+ add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+ add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+ addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+@@ -128,8 +128,8 @@ sh3:
+ rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+ sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
+ sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+ shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+ shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+diff --git a/gas/testsuite/gas/sh/arch/sh3e.s b/gas/testsuite/gas/sh/arch/sh3e.s
+index f5c8ab9..215e5ec 100644
+--- a/gas/testsuite/gas/sh/arch/sh3e.s
++++ b/gas/testsuite/gas/sh/arch/sh3e.s
+@@ -12,7 +12,7 @@
+ sh3e:
+ ! Instructions introduced into sh3e
+
+-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu
++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-or-sh3e sh2e sh3 sh3-nommu
+ add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+ add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+ addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+@@ -132,8 +132,8 @@ sh3e:
+ rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+ sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
+ sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+ shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+ shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+diff --git a/gas/testsuite/gas/sh/arch/sh4-nofpu.s b/gas/testsuite/gas/sh/arch/sh4-nofpu.s
+index 32b58f9..1fef035 100644
+--- a/gas/testsuite/gas/sh/arch/sh4-nofpu.s
++++ b/gas/testsuite/gas/sh/arch/sh4-nofpu.s
+@@ -12,7 +12,7 @@
+ sh4_nofpu:
+ ! Instructions introduced into sh4-nofpu
+
+-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
+ add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+ add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+ addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+@@ -136,8 +136,8 @@ sh4_nofpu:
+ rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+ sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
+ sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+ shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+ shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+diff --git a/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s b/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s
+index 61f0bc6..65d11c5 100644
+--- a/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s
++++ b/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s
+@@ -24,7 +24,7 @@ sh4_nommu_nofpu:
+ stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
+ stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
+
+-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
+ add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+ add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+ addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+@@ -139,8 +139,8 @@ sh4_nommu_nofpu:
+ rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+ sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
+ sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+ shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+ shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+diff --git a/gas/testsuite/gas/sh/arch/sh4.s b/gas/testsuite/gas/sh/arch/sh4.s
+index af135ce..dc199cb 100644
+--- a/gas/testsuite/gas/sh/arch/sh4.s
++++ b/gas/testsuite/gas/sh/arch/sh4.s
+@@ -17,7 +17,7 @@ sh4:
+ fsrra fr1 ;!/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}
+ ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}
+
+-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
+ add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+ add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+ addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+@@ -145,8 +145,8 @@ sh4:
+ rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+ sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
+ sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+ shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+ shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+diff --git a/gas/testsuite/gas/sh/arch/sh4a-nofpu.s b/gas/testsuite/gas/sh/arch/sh4a-nofpu.s
+index 9522bb6..7581f47 100644
+--- a/gas/testsuite/gas/sh/arch/sh4a-nofpu.s
++++ b/gas/testsuite/gas/sh/arch/sh4a-nofpu.s
+@@ -19,7 +19,7 @@ sh4a_nofpu:
+ prefi @r4 ;!/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up}
+ synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up}
+
+-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
+ add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+ add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+ addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+@@ -143,8 +143,8 @@ sh4a_nofpu:
+ rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+ sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
+ sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+ shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+ shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+diff --git a/gas/testsuite/gas/sh/arch/sh4a.s b/gas/testsuite/gas/sh/arch/sh4a.s
+index 950ed2d..55e9611 100644
+--- a/gas/testsuite/gas/sh/arch/sh4a.s
++++ b/gas/testsuite/gas/sh/arch/sh4a.s
+@@ -13,7 +13,7 @@ sh4a:
+ ! Instructions introduced into sh4a
+ fpchg ;!/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}
+
+-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
++! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
+ add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+ add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+ addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+@@ -147,8 +147,8 @@ sh4a:
+ rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+ sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
+ sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+ shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+ shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+diff --git a/gas/testsuite/gas/sh/arch/sh4al-dsp.s b/gas/testsuite/gas/sh/arch/sh4al-dsp.s
+index 6caaf2c..fde6c1e 100644
+--- a/gas/testsuite/gas/sh/arch/sh4al-dsp.s
++++ b/gas/testsuite/gas/sh/arch/sh4al-dsp.s
+@@ -48,7 +48,7 @@ sh4al_dsp:
+ dct pswap x1,m0 ;!/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */ {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up}
+ dct pswap y0,m0 ;!/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */ {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up}
+
+-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
++! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
+ add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+ add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+ addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+@@ -202,8 +202,8 @@ sh4al_dsp:
+ setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
+ repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
+ repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
+- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
++ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
++ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
+ shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+ shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+ shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+diff --git a/include/elf/sh.h b/include/elf/sh.h
+index a54158f..109d90f 100644
+--- a/include/elf/sh.h
++++ b/include/elf/sh.h
+@@ -35,6 +35,7 @@
+ #define EF_SH2E 11
+ #define EF_SH4A 12
+ #define EF_SH2A 13
++#define EF_SHJ2 14
+
+ #define EF_SH4_NOFPU 16
+ #define EF_SH4A_NOFPU 17
+@@ -46,6 +47,7 @@
+ #define EF_SH2A_SH3_NOFPU 22
+ #define EF_SH2A_SH4 23
+ #define EF_SH2A_SH3E 24
++#define EF_SH2A_SH3_SHJ2 25
+
+ /* This one can only mix in objects from other EF_SH5 objects. */
+ #define EF_SH5 10
+@@ -68,7 +70,8 @@
+ /* EF_SH2E */ bfd_mach_sh2e , \
+ /* EF_SH4A */ bfd_mach_sh4a , \
+ /* EF_SH2A */ bfd_mach_sh2a , \
+-/* 14, 15 */ 0, 0, \
++/* EF_SHJ2 */ bfd_mach_shj2 , \
++/* 15 */ 0, \
+ /* EF_SH4_NOFPU */ bfd_mach_sh4_nofpu , \
+ /* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \
+ /* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \
+@@ -77,7 +80,8 @@
+ /* EF_SH2A_SH4_NOFPU */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \
+ /* EF_SH2A_SH3_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \
+ /* EF_SH2A_SH4 */ bfd_mach_sh2a_or_sh4 , \
+-/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e
++/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e, \
++/* EF_SH2A_SH3_SHJ2_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu
+
+ /* Convert arch_sh* into EF_SH*. */
+ int sh_find_elf_flags (unsigned int arch_set);
+diff --git a/opcodes/sh-dis.c b/opcodes/sh-dis.c
+index d4e1a6d..181e21a 100644
+--- a/opcodes/sh-dis.c
++++ b/opcodes/sh-dis.c
+@@ -868,6 +868,9 @@ print_insn_sh (bfd_vma memaddr, struct disassemble_info *info)
+ case XMTRX_M4:
+ fprintf_fn (stream, "xmtrx");
+ break;
++ case A_IND_0:
++ fprintf_fn (stream, "@r0");
++ break;
+ default:
+ abort ();
+ }
+diff --git a/opcodes/sh-opc.h b/opcodes/sh-opc.h
+index 5863aa9..19c5a61 100644
+--- a/opcodes/sh-opc.h
++++ b/opcodes/sh-opc.h
+@@ -187,7 +187,8 @@ typedef enum
+ FPUL_N,
+ FPUL_M,
+ FPSCR_N,
+- FPSCR_M
++ FPSCR_M,
++ A_IND_0
+ }
+ sh_arg_type;
+
+@@ -214,9 +215,11 @@ sh_dsp_reg_nums;
+ #define arch_sh4_base (1 << 5)
+ #define arch_sh4a_base (1 << 6)
+ #define arch_sh2a_base (1 << 7)
+-#define arch_sh_base_mask MASK (0, 7)
++#define arch_shj2_base (1 << 8)
++#define arch_sh2a_sh3_shj2_base (1 << 9)
++#define arch_sh_base_mask MASK (0, 9)
+
+-/* Bits 8 ... 24 are currently free. */
++/* Bits 10 ... 24 are currently free. */
+
+ /* This is an annotation on instruction types, but we
+ abuse the arch field in instructions to denote it. */
+@@ -254,6 +257,8 @@ sh_dsp_reg_nums;
+ #define arch_sh2a_nofpu_or_sh3_nommu (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co)
+ #define arch_sh2a_or_sh3e (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu)
+ #define arch_sh2a_or_sh4 (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu)
++#define arch_shj2 (arch_shj2_base |arch_sh_no_mmu |arch_sh_no_co)
++#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu (arch_sh2a_sh3_shj2_base|arch_sh_no_mmu |arch_sh_no_co)
+
+ #define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2))
+ #define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0)
+@@ -319,7 +324,8 @@ SH4AL-dsp SH4A
+ #define arch_sh2_up (arch_sh2 \
+ | arch_sh2e_up \
+ | arch_sh2a_nofpu_or_sh3_nommu_up \
+- | arch_sh_dsp_up)
++ | arch_sh_dsp_up \
++ | arch_shj2_up)
+ #define arch_sh2a_nofpu_or_sh3_nommu_up (arch_sh2a_nofpu_or_sh3_nommu \
+ | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
+ | arch_sh2a_or_sh3e_up \
+@@ -345,6 +351,12 @@ SH4AL-dsp SH4A
+ #define arch_sh4a_nofpu_up (arch_sh4a_nofpu \
+ | arch_sh4a_up \
+ | arch_sh4al_dsp_up)
++#define arch_shj2_up ( arch_shj2)
++#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up (arch_sh2a_nofpu_or_sh3_nommu \
++ | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
++ | arch_sh2a_or_sh3e_up \
++ | arch_sh3_nommu_up \
++ | arch_shj2_up)
+
+ /* Right branches. */
+ #define arch_sh2e_up (arch_sh2e \
+@@ -713,9 +725,9 @@ const sh_opcode_info sh_table[] =
+
+ /* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up},
+
+-/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up},
++/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
+
+-/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up},
++/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
+
+ /* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up},
+
+@@ -1193,7 +1205,7 @@ const sh_opcode_info sh_table[] =
+ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32},
+ /* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */
+ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32},
+-
++ /* 0010nnnnmmmm0011 cas.l Rm,Rn,@R0 */ {"cas.l", { A_REG_M,A_REG_N,A_IND_0},{HEX_2,REG_N,REG_M,HEX_3}, arch_shj2_up},
+ { 0, {0}, {0}, 0 }
+ };
+
--- /dev/null
+diff -ur ../baseline/binutils-2.25.1/bfd/config.bfd binutils-2.25.1/bfd/config.bfd
+--- ../baseline/binutils-2.25.1/bfd/config.bfd 2014-10-14 07:32:02.000000000 +0000
++++ binutils-2.25.1/bfd/config.bfd 2015-09-04 19:24:08.678337083 +0000
+@@ -1370,6 +1370,7 @@
+ sh-*-linux*)
+ targ_defvec=sh_elf32_linux_be_vec
+ targ_selvecs="sh_elf32_linux_vec sh64_elf32_linux_vec sh64_elf32_linux_be_vec sh64_elf64_linux_vec sh64_elf64_linux_be_vec"
++ targ_selvecs="${targ_selvecs} sh_elf32_vec sh_elf32_le_vec sh_elf32_fdpic_le_vec sh_elf32_fdpic_be_vec"
+ want64=true
+ ;;
+ #endif /* BFD64 */
+@@ -1377,10 +1378,12 @@
+ sh*eb-*-linux*)
+ targ_defvec=sh_elf32_linux_be_vec
+ targ_selvecs=sh_elf32_linux_vec
++ targ_selvecs="${targ_selvecs} sh_elf32_vec sh_elf32_le_vec sh_elf32_fdpic_le_vec sh_elf32_fdpic_be_vec"
+ ;;
+ sh*-*-linux*)
+ targ_defvec=sh_elf32_linux_vec
+ targ_selvecs=sh_elf32_linux_be_vec
++ targ_selvecs="${targ_selvecs} sh_elf32_vec sh_elf32_le_vec sh_elf32_fdpic_le_vec sh_elf32_fdpic_be_vec"
+ ;;
+
+ sh-*-uclinux* | sh[12]-*-uclinux*)
+diff -ur ../baseline/binutils-2.25.1/ld/configure.tgt binutils-2.25.1/ld/configure.tgt
+--- ../baseline/binutils-2.25.1/ld/configure.tgt 2014-10-14 07:32:04.000000000 +0000
++++ binutils-2.25.1/ld/configure.tgt 2015-09-04 19:22:05.151677949 +0000
+@@ -623,15 +623,17 @@
+ score-*-elf) targ_emul=score7_elf
+ targ_extra_emuls=score3_elf ;;
+ sh-*-linux*) targ_emul=shlelf_linux
+- targ_extra_emuls=shelf_linux
++ targ_extra_emuls="shelf_linux shlelf_fd shelf_fd shlelf shelf"
+ targ_extra_libpath=shelf_linux ;;
+ sh64eb-*-linux*) targ_emul=shelf32_linux
+ targ_extra_emuls="shlelf32_linux" ;;
+ sh64-*-linux*) targ_emul=shlelf32_linux
+ targ_extra_emuls="shelf32_linux"
+ targ_extra_libpath=shelf32_linux ;;
+-sh*eb-*-linux*) targ_emul=shelf_linux ;;
+-sh*-*-linux*) targ_emul=shlelf_linux ;;
++sh*eb-*-linux*) targ_emul=shelf_linux
++ targ_extra_emuls="shelf_fd shelf" ;;
++sh*-*-linux*) targ_emul=shlelf_linux
++ targ_extra_emuls="shlelf_fd shlelf" ;;
+ sh5le-*-netbsd*) targ_emul=shlelf32_nbsd
+ targ_extra_emuls="shelf32_nbsd shelf64_nbsd shlelf64_nbsd shelf_nbsd shlelf_nbsd" ;;
+ sh5-*-netbsd*) targ_emul=shelf32_nbsd
--- /dev/null
+diff -ur binutils-2.25.1.orig/bfd/elf32-sh.c binutils-2.25.1/bfd/elf32-sh.c
+--- binutils-2.25.1.orig/bfd/elf32-sh.c 2015-09-03 21:52:17.000000000 +0000
++++ binutils-2.25.1/bfd/elf32-sh.c 2015-09-14 17:08:48.114426847 +0000
+@@ -5487,7 +5487,7 @@
+ input_bfd, input_section, rel->r_offset, symname);
+ }
+
+- elf_elfheader (output_bfd)->e_flags &= ~EF_SH_PIC;
++ elf_elfheader (output_bfd)->e_flags |= EF_SH_PIC;
+ }
+
+ if (r != bfd_reloc_ok)
+@@ -6644,7 +6644,7 @@
+ elf_elfheader (obfd)->e_flags = elf_elfheader (ibfd)->e_flags;
+ sh_elf_set_mach_from_flags (obfd);
+ if (elf_elfheader (obfd)->e_flags & EF_SH_FDPIC)
+- elf_elfheader (obfd)->e_flags |= EF_SH_PIC;
++ elf_elfheader (obfd)->e_flags &= ~EF_SH_PIC;
+ }
+
+ if (! sh_merge_bfd_arch (ibfd, obfd))
--- /dev/null
+--- binutils-2.25.1/bfd/elf32-sh.c.orig 2015-10-08 16:33:04.413334344 +0000
++++ binutils-2.25.1/bfd/elf32-sh.c 2015-10-08 16:23:05.709980166 +0000
+@@ -3604,7 +3604,7 @@ sh_elf_size_dynamic_sections (bfd *outpu
+ return FALSE;
+ }
+ else if ((elf_elfheader (output_bfd)->e_flags & EF_SH_FDPIC)
+- && htab->sgot->size != 0)
++ /* && htab->sgot->size != 0 */)
+ {
+ if (! add_dynamic_entry (DT_PLTGOT, 0))
+ return FALSE;
--- /dev/null
+--- binutils-2.25.1/bfd/elf32-microblaze.c.orig 2016-02-11 23:12:00.301992882 +0000
++++ binutils-2.25.1/bfd/elf32-microblaze.c 2016-02-11 23:28:12.043074209 +0000
+@@ -3293,8 +3293,7 @@
+ The entry in the global offset table will already have been
+ initialized in the relocate_section function. */
+ if (info->shared
+- && (info->symbolic || h->dynindx == -1)
+- && h->def_regular)
++ && ((info->symbolic && h->def_regular) || h->dynindx == -1))
+ {
+ asection *sec = h->root.u.def.section;
+ microblaze_elf_output_dynamic_relocation (output_bfd,
--- /dev/null
+From d840c081f8082e8b9e63fead5306643975a97bb3 Mon Sep 17 00:00:00 2001
+From: Richard Earnshaw <Richard.Earnshaw@arm.com>
+Date: Thu, 20 Nov 2014 17:02:47 +0000
+Subject: [PATCH] * config/tc-arm.c (rotate_left): Avoid undefined behaviour
+ when N = 0.
+
+---
+
+diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
+index 5077f87..9100fb2 100644
+--- a/gas/config/tc-arm.c
++++ b/gas/config/tc-arm.c
+@@ -7251,7 +7251,7 @@ parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
+
+ /* Functions for operand encoding. ARM, then Thumb. */
+
+-#define rotate_left(v, n) (v << n | v >> (32 - n))
++#define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
+
+ /* If VAL can be encoded in the immediate field of an ARM instruction,
+ return the encoded form. Otherwise, return FAIL. */
--- /dev/null
+diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
+index bd4b576..41803c2 100644
+--- a/bfd/elf32-arm.c
++++ b/bfd/elf32-arm.c
+@@ -13786,7 +13786,7 @@ elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+diff --git a/bfd/elf32-bfin.c b/bfd/elf32-bfin.c
+index 49ef360..8346d57 100644
+--- a/bfd/elf32-bfin.c
++++ b/bfd/elf32-bfin.c
+@@ -4257,7 +4257,7 @@ elf32_bfinfdpic_size_dynamic_sections (bfd *output_bfd,
+ if (htab->dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+diff --git a/bfd/elf32-cris.c b/bfd/elf32-cris.c
+index 3031173..5b40524 100644
+--- a/bfd/elf32-cris.c
++++ b/bfd/elf32-cris.c
+@@ -3764,7 +3764,7 @@ elf_cris_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+diff --git a/bfd/elf32-frv.c b/bfd/elf32-frv.c
+index b55a7ab..ef72c23 100644
+--- a/bfd/elf32-frv.c
++++ b/bfd/elf32-frv.c
+@@ -5444,7 +5444,7 @@ elf32_frvfdpic_size_dynamic_sections (bfd *output_bfd,
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+diff --git a/bfd/elf32-hppa.c b/bfd/elf32-hppa.c
+index 41bf5c5..62c7cf6 100644
+--- a/bfd/elf32-hppa.c
++++ b/bfd/elf32-hppa.c
+@@ -2215,7 +2215,7 @@ elf32_hppa_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
+ if (htab->etab.dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ sec = bfd_get_linker_section (dynobj, ".interp");
+ if (sec == NULL)
+diff --git a/bfd/elf32-i370.c b/bfd/elf32-i370.c
+index 7fba4d1..458f694 100644
+--- a/bfd/elf32-i370.c
++++ b/bfd/elf32-i370.c
+@@ -594,7 +594,7 @@ i370_elf_size_dynamic_sections (bfd *output_bfd,
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+diff --git a/bfd/elf32-i386.c b/bfd/elf32-i386.c
+index 7642d0f..b0844c8 100644
+--- a/bfd/elf32-i386.c
++++ b/bfd/elf32-i386.c
+@@ -2834,7 +2834,7 @@ elf_i386_size_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info)
+ if (htab->elf.dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ if (s == NULL)
+diff --git a/bfd/elf32-m32r.c b/bfd/elf32-m32r.c
+index 155d079..a2e3c7c 100644
+--- a/bfd/elf32-m32r.c
++++ b/bfd/elf32-m32r.c
+@@ -2170,7 +2170,7 @@ m32r_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
+ if (htab->root.dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+diff --git a/bfd/elf32-m68k.c b/bfd/elf32-m68k.c
+index 10d2fcb..489f3f1 100644
+--- a/bfd/elf32-m68k.c
++++ b/bfd/elf32-m68k.c
+@@ -3257,7 +3257,7 @@ elf_m68k_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+diff --git a/bfd/elf32-ppc.c b/bfd/elf32-ppc.c
+index 8415f1e..5597051 100644
+--- a/bfd/elf32-ppc.c
++++ b/bfd/elf32-ppc.c
+@@ -6191,7 +6191,7 @@ ppc_elf_size_dynamic_sections (bfd *output_bfd,
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (htab->elf.dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+diff --git a/bfd/elf32-s390.c b/bfd/elf32-s390.c
+index de37ca4..a1e628c 100644
+--- a/bfd/elf32-s390.c
++++ b/bfd/elf32-s390.c
+@@ -2039,7 +2039,7 @@ elf_s390_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
+ if (htab->elf.dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ if (s == NULL)
+diff --git a/bfd/elf32-sh.c b/bfd/elf32-sh.c
+index 012ee4e..a51453f 100644
+--- a/bfd/elf32-sh.c
++++ b/bfd/elf32-sh.c
+@@ -3349,7 +3349,7 @@ sh_elf_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
+ if (htab->root.dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+diff --git a/bfd/elf32-vax.c b/bfd/elf32-vax.c
+index 6089e8c..893ea8d 100644
+--- a/bfd/elf32-vax.c
++++ b/bfd/elf32-vax.c
+@@ -1124,7 +1124,7 @@ elf_vax_size_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info)
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+diff --git a/bfd/elf32-xtensa.c b/bfd/elf32-xtensa.c
+index 73538cd..37ea5da 100644
+--- a/bfd/elf32-xtensa.c
++++ b/bfd/elf32-xtensa.c
+@@ -1637,7 +1637,7 @@ elf_xtensa_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
+ && htab->sgotloc != NULL);
+
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ if (s == NULL)
+diff --git a/bfd/elf64-alpha.c b/bfd/elf64-alpha.c
+index f67b0af..1973cd0 100644
+--- a/bfd/elf64-alpha.c
++++ b/bfd/elf64-alpha.c
+@@ -2877,7 +2877,7 @@ elf64_alpha_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+diff --git a/bfd/elf64-hppa.c b/bfd/elf64-hppa.c
+index 6f40b88..3b628b4 100644
+--- a/bfd/elf64-hppa.c
++++ b/bfd/elf64-hppa.c
+@@ -1558,7 +1558,7 @@ elf64_hppa_size_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info)
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ sec = bfd_get_linker_section (dynobj, ".interp");
+ BFD_ASSERT (sec != NULL);
+diff --git a/bfd/elf64-ppc.c b/bfd/elf64-ppc.c
+index 8cff990..851845f 100644
+--- a/bfd/elf64-ppc.c
++++ b/bfd/elf64-ppc.c
+@@ -9748,7 +9748,7 @@ ppc64_elf_size_dynamic_sections (bfd *output_bfd,
+ if (htab->elf.dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ if (s == NULL)
+diff --git a/bfd/elf64-s390.c b/bfd/elf64-s390.c
+index 2e505f3..406bb66 100644
+--- a/bfd/elf64-s390.c
++++ b/bfd/elf64-s390.c
+@@ -1989,7 +1989,7 @@ elf_s390_size_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
+ if (htab->elf.dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ if (s == NULL)
+diff --git a/bfd/elf64-sh64.c b/bfd/elf64-sh64.c
+index e460895..d920598 100644
+--- a/bfd/elf64-sh64.c
++++ b/bfd/elf64-sh64.c
+@@ -3404,7 +3404,7 @@ sh64_elf64_size_dynamic_sections (bfd *output_bfd,
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+diff --git a/bfd/elf64-x86-64.c b/bfd/elf64-x86-64.c
+index f15d33e..870aadf 100644
+--- a/bfd/elf64-x86-64.c
++++ b/bfd/elf64-x86-64.c
+@@ -3181,7 +3181,7 @@ elf_x86_64_size_dynamic_sections (bfd *output_bfd,
+ if (htab->elf.dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ if (s == NULL)
+diff --git a/bfd/elflink.c b/bfd/elflink.c
+index 7f04271..5b3438d 100644
+--- a/bfd/elflink.c
++++ b/bfd/elflink.c
+@@ -246,7 +246,7 @@ _bfd_elf_link_create_dynamic_sections (bfd *abfd, struct bfd_link_info *info)
+
+ /* A dynamically linked executable has a .interp section, but a
+ shared library does not. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_make_section_anyway_with_flags (abfd, ".interp",
+ flags | SEC_READONLY);
+@@ -5763,7 +5763,7 @@ bfd_elf_size_dynamic_sections (bfd *output_bfd,
+ bfd_boolean all_defined;
+
+ *sinterpptr = bfd_get_section_by_name (dynobj, ".interp");
+- BFD_ASSERT (*sinterpptr != NULL || !info->executable);
++ BFD_ASSERT (*sinterpptr != NULL || !info->executable || info->nointerp);
+
+ if (soname != NULL)
+ {
+diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
+index be1e59a..329dec3 100644
+--- a/bfd/elfxx-mips.c
++++ b/bfd/elfxx-mips.c
+@@ -9579,7 +9579,7 @@ _bfd_mips_elf_size_dynamic_sections (bfd *output_bfd,
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+diff --git a/bfd/elfxx-sparc.c b/bfd/elfxx-sparc.c
+index 9bb71a9..db0d4f1 100644
+--- a/bfd/elfxx-sparc.c
++++ b/bfd/elfxx-sparc.c
+@@ -2559,7 +2559,7 @@ _bfd_sparc_elf_size_dynamic_sections (bfd *output_bfd,
+ if (elf_hash_table (info)->dynamic_sections_created)
+ {
+ /* Set the contents of the .interp section to the interpreter. */
+- if (info->executable)
++ if (info->executable && !info->nointerp)
+ {
+ s = bfd_get_linker_section (dynobj, ".interp");
+ BFD_ASSERT (s != NULL);
+diff --git a/include/bfdlink.h b/include/bfdlink.h
+index 797a465..cf533dd 100644
+--- a/include/bfdlink.h
++++ b/include/bfdlink.h
+@@ -433,6 +433,9 @@ struct bfd_link_info
+ /* TRUE if BND prefix in PLT entries is always generated. */
+ unsigned int bndplt: 1;
+
++ /* TRUE if generation of .interp/PT_INTERP should be suppressed. */
++ unsigned int nointerp: 1;
++
+ /* Char that may appear as the first char of a symbol, but should be
+ skipped (like symbol_leading_char) when looking up symbols in
+ wrap_hash. Used by PowerPC Linux for 'dot' symbols. */
+diff --git a/ld/ld.texinfo b/ld/ld.texinfo
+index cf3b586..1e5e5cf 100644
+--- a/ld/ld.texinfo
++++ b/ld/ld.texinfo
+@@ -1426,6 +1426,13 @@ generating dynamically linked ELF executables. The default dynamic
+ linker is normally correct; don't use this unless you know what you are
+ doing.
+
++@kindex --no-dynamic-linker
++@item --no-dynamic-linker
++When producing an executable file, omit the request for a dynamic
++linker to be used at load-time. This is only meaningful for ELF
++executables that contain dynamic relocations, and usually requires
++entry point code that is capable of processing these relocations.
++
+ @kindex --fatal-warnings
+ @kindex --no-fatal-warnings
+ @item --fatal-warnings
+diff --git a/ld/lexsup.c b/ld/lexsup.c
+index 59bd14f..8b57f84 100644
+--- a/ld/lexsup.c
++++ b/ld/lexsup.c
+@@ -33,6 +33,7 @@ enum option_values
+ OPTION_DEFSYM,
+ OPTION_DEMANGLE,
+ OPTION_DYNAMIC_LINKER,
++ OPTION_NO_DYNAMIC_LINKER,
+ OPTION_SYSROOT,
+ OPTION_EB,
+ OPTION_EL,
+diff --git a/ld/lexsup.c b/ld/lexsup.c
+index 777d6e2..1b992f7 100644
+--- a/ld/lexsup.c
++++ b/ld/lexsup.c
+@@ -138,6 +138,9 @@ static const struct ld_option ld_options[] =
+ { {"dynamic-linker", required_argument, NULL, OPTION_DYNAMIC_LINKER},
+ 'I', N_("PROGRAM"), N_("Set PROGRAM as the dynamic linker to use"),
+ TWO_DASHES },
++ { {"no-dynamic-linker", no_argument, NULL, OPTION_NO_DYNAMIC_LINKER},
++ '\0', NULL, N_("Produce an executable with no program interpreter header"),
++ TWO_DASHES },
+ { {"library", required_argument, NULL, 'l'},
+ 'l', N_("LIBNAME"), N_("Search for library LIBNAME"), TWO_DASHES },
+ { {"library-path", required_argument, NULL, 'L'},
+@@ -762,6 +765,10 @@ parse_args (unsigned argc, char **argv)
+ case 'I': /* Used on Solaris. */
+ case OPTION_DYNAMIC_LINKER:
+ command_line.interpreter = optarg;
++ link_info.nointerp = 0;
++ break;
++ case OPTION_NO_DYNAMIC_LINKER:
++ link_info.nointerp = 1;
+ break;
+ case OPTION_SYSROOT:
+ /* Already handled in ldmain.c. */
--- /dev/null
+The binutils build notices that makeinfo is missing, but fails anyway, breaking
+the build. Make it stop.
+
+The "info" file format is obsolete (similar to "gopher"), was never used
+by anyone but the FSF, and failed to even replace man pages (which are
+now available in HTML).
+
+--- binutils-2.18/missing 2005-07-13 20:24:56.000000000 -0500
++++ binutils-2.18/missing 2008-08-11 02:05:47.000000000 -0500
+@@ -299,7 +299,7 @@
+ fi
+ # If the file does not exist, the user really needs makeinfo;
+ # let's fail without touching anything.
+- test -f $file || exit 1
++ test -f $file || exit 0
+ touch $file
+ ;;
+
--- /dev/null
+--- binutils-397a64b3.orig//gas/config/tc-sh.c 2015-08-11 01:29:26.000000000 +0000
++++ binutils-397a64b3/gas/config/tc-sh.c 2015-11-02 23:17:03.931462591 +0000
+@@ -4491,6 +4496,8 @@ sh_parse_name (char const *name,
+ reloc_type = BFD_RELOC_SH_TLS_LE_32;
+ else if ((next_end = sh_end_of_match (next + 1, "DTPOFF")))
+ reloc_type = BFD_RELOC_SH_TLS_LDO_32;
++ else if ((next_end = sh_end_of_match (next + 1, "PCREL")))
++ reloc_type = BFD_RELOC_32_PCREL;
+ else
+ goto no_suffix;
+
--- /dev/null
+diff --git a/config.sub b/config.sub
+index fab0aa3..b83660a 100755
+--- a/config.sub
++++ b/config.sub
+@@ -120,7 +120,7 @@ esac
+ # Here we must recognize all the valid KERNEL-OS combinations.
+ maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'`
+ case $maybe_os in
+- nto-qnx* | linux-gnu* | linux-dietlibc | linux-newlib* | linux-uclibc* | \
++ nto-qnx* | linux-gnu* | linux-dietlibc | linux-newlib* | linux-uclibc* | linux-musl* | \
+ uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | knetbsd*-gnu* | netbsd*-gnu* | \
+ storm-chaos* | os2-emx* | rtmk-nova*)
+ os=-$maybe_os
+@@ -1211,7 +1211,7 @@ case $os in
+ | -udi* | -eabi* | -lites* | -ieee* | -go32* | -aux* \
+ | -chorusos* | -chorusrdb* \
+ | -cygwin* | -pe* | -psos* | -moss* | -proelf* | -rtems* \
+- | -mingw32* | -linux-gnu* | -linux-newlib* | -linux-uclibc* \
++ | -mingw32* | -linux-gnu* | -linux-newlib* | -linux-uclibc* | -linux-musl* \
+ | -uxpv* | -beos* | -mpeix* | -udk* \
+ | -interix* | -uwin* | -mks* | -rhapsody* | -darwin* | -opened* \
+ | -openstep* | -oskit* | -conix* | -pw32* | -nonstopux* \
+diff --git a/fixincludes/mkfixinc.sh b/fixincludes/mkfixinc.sh
+index ef048f7..f1cb8a5 100755
+--- a/fixincludes/mkfixinc.sh
++++ b/fixincludes/mkfixinc.sh
+@@ -28,7 +28,8 @@ case $machine in
+ powerpc-*-eabi* | \
+ powerpc-*-rtems* | \
+ powerpcle-*-eabisim* | \
+- powerpcle-*-eabi* )
++ powerpcle-*-eabi* | \
++ *-musl* )
+ # IF there is no include fixing,
+ # THEN create a no-op fixer and exit
+ (echo "#! /bin/sh" ; echo "exit 0" ) > ${target}
+diff --git a/gcc/config.gcc b/gcc/config.gcc
+index 9a142e2..25136b7 100644
+--- a/gcc/config.gcc
++++ b/gcc/config.gcc
+@@ -468,11 +468,14 @@ case ${target} in
+ esac
+ tmake_file="t-slibgcc-elf-ver t-linux"
+ case ${target} in
++ *-*-*musl*)
++ tm_defines="${tm_defines} UCLIBC_DEFAULT=0 MUSL_DEFAULT=1"
++ ;;
+ *-*-*uclibc*)
+- tm_defines="${tm_defines} UCLIBC_DEFAULT=1"
++ tm_defines="${tm_defines} UCLIBC_DEFAULT=1 MUSL_DEFAULT=0"
+ ;;
+ *)
+- tm_defines="${tm_defines} UCLIBC_DEFAULT=0"
++ tm_defines="${tm_defines} UCLIBC_DEFAULT=0 MUSL_DEFAULT=0"
+ ;;
+ esac
+ # Assume that glibc or uClibc are being used and so __cxa_atexit is provided.
+diff --git a/gcc/config/arm/linux-eabi.h b/gcc/config/arm/linux-eabi.h
+index 6612f74..f2ce735 100644
+--- a/gcc/config/arm/linux-eabi.h
++++ b/gcc/config/arm/linux-eabi.h
+@@ -55,6 +55,23 @@
+ #undef GLIBC_DYNAMIC_LINKER
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.3"
+
++/* For ARM musl currently supports four dynamic linkers:
++ - ld-musl-arm.so.1 - for the EABI-derived soft-float ABI
++ - ld-musl-armhf.so.1 - for the EABI-derived hard-float ABI
++ - ld-musl-armeb.so.1 - for the EABI-derived soft-float ABI, EB
++ - ld-musl-armebhf.so.1 - for the EABI-derived hard-float ABI, EB
++ musl does not support the legacy OABI mode.
++ All the dynamic linkers live in /lib.
++ We default to soft-float, EL. */
++#undef MUSL_DYNAMIC_LINKER
++#if TARGET_BIG_ENDIAN_DEFAULT
++#define MUSL_DYNAMIC_LINKER_E "%{mlittle-endian:;:eb}"
++#else
++#define MUSL_DYNAMIC_LINKER_E "%{mbig-endian:eb}"
++#endif
++#define MUSL_DYNAMIC_LINKER \
++ "/lib/ld-musl-arm" MUSL_DYNAMIC_LINKER_E "%{mfloat-abi=hard:hf}.so.1"
++
+ /* At this point, bpabi.h will have clobbered LINK_SPEC. We want to
+ use the GNU/Linux version, not the generic BPABI version. */
+ #undef LINK_SPEC
+diff --git a/gcc/config/i386/linux.h b/gcc/config/i386/linux.h
+index 7eb2395..213b586 100644
+--- a/gcc/config/i386/linux.h
++++ b/gcc/config/i386/linux.h
+@@ -103,6 +103,9 @@ Boston, MA 02110-1301, USA. */
+ #define LINK_EMULATION "elf_i386"
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
+
++#undef MUSL_DYNAMIC_LINKER
++#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-i386.so.1"
++
+ #undef SUBTARGET_EXTRA_SPECS
+ #define SUBTARGET_EXTRA_SPECS \
+ { "link_emulation", LINK_EMULATION },\
+diff --git a/gcc/config/i386/linux64.h b/gcc/config/i386/linux64.h
+index cc8ed16..f0f025e 100644
+--- a/gcc/config/i386/linux64.h
++++ b/gcc/config/i386/linux64.h
+@@ -52,6 +52,13 @@ Boston, MA 02110-1301, USA. */
+ #define GLIBC_DYNAMIC_LINKER32 "/lib/ld-linux.so.2"
+ #define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux-x86-64.so.2"
+
++#undef MUSL_DYNAMIC_LINKER32
++#define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-i386.so.1"
++#undef MUSL_DYNAMIC_LINKER64
++#define MUSL_DYNAMIC_LINKER64 "/lib/ld-musl-x86_64.so.1"
++#undef MUSL_DYNAMIC_LINKERX32
++#define MUSL_DYNAMIC_LINKERX32 "/lib/ld-musl-x32.so.1"
++
+ #undef LINK_SPEC
+ #define LINK_SPEC "%{!m32:-m elf_x86_64} %{m32:-m elf_i386} \
+ %{shared:-shared} \
+diff --git a/gcc/config/linux.h b/gcc/config/linux.h
+index 59e3e85..1967b46 100644
+--- a/gcc/config/linux.h
++++ b/gcc/config/linux.h
+@@ -102,10 +102,12 @@ Boston, MA 02110-1301, USA. */
+ /* Determine which dynamic linker to use depending on whether GLIBC or
+ uClibc is the default C library and whether -muclibc or -mglibc has
+ been passed to change the default. */
+-#if UCLIBC_DEFAULT
+-#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:%{muclibc:%e-mglibc and -muclibc used together}" G ";:" U "}"
++#if MUSL_DEFAULT
++#define CHOOSE_DYNAMIC_LINKER(G, U, M) "%{mglibc:" G ";muclibc:" U ";:" M "}"
++#elif UCLIBC_DEFAULT
++#define CHOOSE_DYNAMIC_LINKER(G, U, M) "%{mglibc:" G ";mmusl:" M ";:" U "}"
+ #else
+-#define CHOOSE_DYNAMIC_LINKER(G, U) "%{muclibc:%{mglibc:%e-mglibc and -muclibc used together}" U ";:" G "}"
++#define CHOOSE_DYNAMIC_LINKER(G, U, M) "%{mmusl:" M ";muclibc:" U ";:" G "}"
+ #endif
+
+ /* For most targets the following definitions suffice;
+@@ -115,15 +117,89 @@ Boston, MA 02110-1301, USA. */
+ #define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
+ #define UCLIBC_DYNAMIC_LINKER32 "/lib/ld-uClibc.so.0"
+ #define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0"
++/* Should be redefined for each target that supports musl. */
++#define MUSL_DYNAMIC_LINKER "/dev/null"
++#define MUSL_DYNAMIC_LINKER32 "/dev/null"
++#define MUSL_DYNAMIC_LINKER64 "/dev/null"
++#define MUSL_DYNAMIC_LINKERX32 "/dev/null"
++
+ #define LINUX_DYNAMIC_LINKER \
+- CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER)
++ CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER, MUSL_DYNAMIC_LINKER)
+ #define LINUX_DYNAMIC_LINKER32 \
+- CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER32, UCLIBC_DYNAMIC_LINKER32)
++ CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER32, UCLIBC_DYNAMIC_LINKER32, MUSL_DYNAMIC_LINKER32)
+ #define LINUX_DYNAMIC_LINKER64 \
+- CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER64, UCLIBC_DYNAMIC_LINKER64)
++ CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER64, UCLIBC_DYNAMIC_LINKER64, MUSL_DYNAMIC_LINKER64)
+
+ /* Determine whether the entire c99 runtime
+ is present in the runtime library. */
+ #define TARGET_C99_FUNCTIONS (OPTION_GLIBC)
+
+ #define TARGET_POSIX_IO
++
++/* musl avoids problematic includes by rearranging the include directories.
++ * Unfortunately, this is mostly duplicated from cppdefault.c */
++#if MUSL_DEFAULT
++#define INCLUDE_DEFAULTS_MUSL_GPP \
++ { GPLUSPLUS_INCLUDE_DIR, "G++", 1, 1, 0, 0 }, \
++ { GPLUSPLUS_TOOL_INCLUDE_DIR, "G++", 1, 1, 0, 1 }, \
++ { GPLUSPLUS_BACKWARD_INCLUDE_DIR, "G++", 1, 1, 0, 0 },
++
++#ifdef LOCAL_INCLUDE_DIR
++#define INCLUDE_DEFAULTS_MUSL_LOCAL \
++ { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 2 }, \
++ { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 0 },
++#else
++#define INCLUDE_DEFAULTS_MUSL_LOCAL
++#endif
++
++#ifdef PREFIX_INCLUDE_DIR
++#define INCLUDE_DEFAULTS_MUSL_PREFIX \
++ { PREFIX_INCLUDE_DIR, 0, 0, 1, 0, 0},
++#else
++#define INCLUDE_DEFAULTS_MUSL_PREFIX
++#endif
++
++#ifdef CROSS_INCLUDE_DIR
++#define INCLUDE_DEFAULTS_MUSL_CROSS \
++ { CROSS_INCLUDE_DIR, "GCC", 0, 0, 0, 0},
++#else
++#define INCLUDE_DEFAULTS_MUSL_CROSS
++#endif
++
++#ifdef TOOL_INCLUDE_DIR
++#define INCLUDE_DEFAULTS_MUSL_TOOL \
++ { TOOL_INCLUDE_DIR, "BINUTILS", 0, 1, 0, 0},
++#else
++#define INCLUDE_DEFAULTS_MUSL_TOOL
++#endif
++
++#ifdef NATIVE_SYSTEM_HEADER_DIR
++#define INCLUDE_DEFAULTS_MUSL_NATIVE \
++ { NATIVE_SYSTEM_HEADER_DIR, 0, 0, 0, 1, 2 }, \
++ { NATIVE_SYSTEM_HEADER_DIR, 0, 0, 0, 1, 0 },
++#else
++#define INCLUDE_DEFAULTS_MUSL_NATIVE
++#endif
++
++#if defined (CROSS_DIRECTORY_STRUCTURE) && !defined (TARGET_SYSTEM_ROOT)
++# undef INCLUDE_DEFAULTS_MUSL_LOCAL
++# define INCLUDE_DEFAULTS_MUSL_LOCAL
++# undef INCLUDE_DEFAULTS_MUSL_NATIVE
++# define INCLUDE_DEFAULTS_MUSL_NATIVE
++#else
++# undef INCLUDE_DEFAULTS_MUSL_CROSS
++# define INCLUDE_DEFAULTS_MUSL_CROSS
++#endif
++
++#undef INCLUDE_DEFAULTS
++#define INCLUDE_DEFAULTS \
++ { \
++ INCLUDE_DEFAULTS_MUSL_GPP \
++ INCLUDE_DEFAULTS_MUSL_PREFIX \
++ INCLUDE_DEFAULTS_MUSL_CROSS \
++ INCLUDE_DEFAULTS_MUSL_TOOL \
++ INCLUDE_DEFAULTS_MUSL_NATIVE \
++ { GCC_INCLUDE_DIR, "GCC", 0, 1, 0, 0 }, \
++ { 0, 0, 0, 0, 0, 0 } \
++ }
++#endif
+diff --git a/gcc/config/linux.opt b/gcc/config/linux.opt
+index 3f615bb..31fb21b 100644
+--- a/gcc/config/linux.opt
++++ b/gcc/config/linux.opt
+@@ -27,3 +27,7 @@ Use uClibc instead of GNU libc
+ mglibc
+ Target RejectNegative Report InverseMask(UCLIBC, GLIBC) Var(linux_uclibc) VarExists
+ Use GNU libc instead of uClibc
++
++mmusl
++Target RejectNegative Report Var(linux_musl)
++Use musl C library
+diff --git a/gcc/config/mips/linux.h b/gcc/config/mips/linux.h
+index ff268d4..97bfc38 100644
+--- a/gcc/config/mips/linux.h
++++ b/gcc/config/mips/linux.h
+@@ -179,3 +179,9 @@ Boston, MA 02110-1301, USA. */
+ %{profile:-lc_p} %{!profile: -lc}}"
+
+ #define MD_UNWIND_SUPPORT "config/mips/linux-unwind.h"
++
++#undef MUSL_DYNAMIC_LINKER32
++#define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-mips%{EL:el}%{msoft-float:-sf}.so.1"
++#undef MUSL_DYNAMIC_LINKER64
++#define MUSL_DYNAMIC_LINKER64 "/lib/ld-musl-mips64%{EL:el}%{msoft-float:-sf}.so.1"
++#define MUSL_DYNAMIC_LINKERN32 "/lib/ld-musl-mipsn32%{EL:el}%{msoft-float:-sf}.so.1"
+diff --git a/gcc/config/sh/linux-unwind.h b/gcc/config/sh/linux-unwind.h
+index de84a77..98d1661 100644
+--- a/gcc/config/sh/linux-unwind.h
++++ b/gcc/config/sh/linux-unwind.h
+@@ -80,10 +80,10 @@ shmedia_fallback_frame_state (struct _Unwind_Context *context,
+ && (*(unsigned long *) (pc+11) == 0x6ff0fff0))
+ {
+ struct rt_sigframe {
+- struct siginfo *pinfo;
++ siginfo_t *pinfo;
+ void *puc;
+- struct siginfo info;
+- struct ucontext uc;
++ siginfo_t info;
++ ucontext_t uc;
+ } *rt_ = context->cfa;
+ /* The void * cast is necessary to avoid an aliasing warning.
+ The aliasing warning is correct, but should not be a problem
+@@ -179,8 +179,8 @@ sh_fallback_frame_state (struct _Unwind_Context *context,
+ && (*(unsigned short *) (pc+14) == 0x00ad))))
+ {
+ struct rt_sigframe {
+- struct siginfo info;
+- struct ucontext uc;
++ siginfo_t info;
++ ucontext_t uc;
+ } *rt_ = context->cfa;
+ /* The void * cast is necessary to avoid an aliasing warning.
+ The aliasing warning is correct, but should not be a problem
+diff --git a/gcc/config/sh/linux.h b/gcc/config/sh/linux.h
+index 94c3166..306a08c 100644
+--- a/gcc/config/sh/linux.h
++++ b/gcc/config/sh/linux.h
+@@ -48,6 +48,29 @@ Boston, MA 02110-1301, USA. */
+
+ #define TARGET_ASM_FILE_END file_end_indicate_exec_stack
+
++#if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
++#define MUSL_DYNAMIC_LINKER_E "%{mb:eb}"
++#else
++#define MUSL_DYNAMIC_LINKER_E "%{!ml:eb}"
++#endif
++
++#if TARGET_CPU_DEFAULT & ( MASK_HARD_SH2A_DOUBLE | MASK_SH4 )
++/* "-nofpu" if any nofpu option is specified */
++#define MUSL_DYNAMIC_LINKER_FP \
++ "%{m1|m2|m2a-nofpu|m3|m4-nofpu|m4-100-nofpu|m4-200-nofpu|m4-300-nofpu|" \
++ "m4-340|m4-400|m4-500|m4al|m5-32media-nofpu|m5-64media-nofpu|" \
++ "m5-compact-nofpu:-nofpu}"
++#else
++/* "-nofpu" if none of the hard fpu options are specified */
++#define MUSL_DYNAMIC_LINKER_FP \
++ "%{m2a|m4|m4-100|m4-200|m4-300|m4a|m5-32media|m5-64media|m5-compact:;:-nofpu}"
++#endif
++
++#undef MUSL_DYNAMIC_LINKER
++#define MUSL_DYNAMIC_LINKER \
++ "/lib/ld-musl-sh" MUSL_DYNAMIC_LINKER_E MUSL_DYNAMIC_LINKER_FP \
++ "%{mfdpic:-fdpic}.so.1"
++
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
+
+ #undef SUBTARGET_LINK_EMUL_SUFFIX
+diff --git a/gcc/unwind-dw2-fde-glibc.c b/gcc/unwind-dw2-fde-glibc.c
+index 25bf2bb..59f7615 100644
+--- a/gcc/unwind-dw2-fde-glibc.c
++++ b/gcc/unwind-dw2-fde-glibc.c
+@@ -49,7 +49,7 @@
+ #include "gthr.h"
+
+ #if !defined(inhibit_libc) && defined(HAVE_LD_EH_FRAME_HDR) \
+- && (__GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ > 2) \
++ && (!defined(__GLIBC__) || __GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ > 2) \
+ || (__GLIBC__ == 2 && __GLIBC_MINOR__ == 2 && defined(DT_CONFIG)))
+
+ #ifndef __RELOC_POINTER
+diff --git a/libstdc++-v3/config/os/generic/os_defines.h b/libstdc++-v3/config/os/generic/os_defines.h
+index bcc533c..a9bfded 100644
+--- a/libstdc++-v3/config/os/generic/os_defines.h
++++ b/libstdc++-v3/config/os/generic/os_defines.h
+@@ -38,4 +38,9 @@
+ // System-specific #define, typedefs, corrections, etc, go here. This
+ // file will come before all others.
+
++// Disable the weak reference logic in gthr.h for os/generic because it
++// is broken on every platform unless there is implementation specific
++// workaround in gthr-posix.h and at link-time for static linking.
++#define _GLIBCXX_GTHREAD_USE_WEAK 0
++
+ #endif
+diff --git a/libstdc++-v3/configure.host b/libstdc++-v3/configure.host
+index 441eb4c..37e80ab 100644
+--- a/libstdc++-v3/configure.host
++++ b/libstdc++-v3/configure.host
+@@ -210,6 +210,9 @@ case "${host_os}" in
+ freebsd*)
+ os_include_dir="os/bsd/freebsd"
+ ;;
++ linux-musl*)
++ os_include_dir="os/generic"
++ ;;
+ gnu* | linux* | kfreebsd*-gnu | knetbsd*-gnu)
+ if [ "$uclibc" = "yes" ]; then
+ os_include_dir="os/uclibc"
--- /dev/null
+diff --git a/gcc/cgraph.c b/gcc/cgraph.c
+index fcdc02e..db04afd 100644
+--- a/gcc/cgraph.c
++++ b/gcc/cgraph.c
+@@ -1169,7 +1169,7 @@ cgraph_function_body_availability (struct cgraph_node *node)
+ inline and offline) having same side effect characteristics as
+ good optimization is what this optimization is about. */
+
+- else if (!(*targetm.binds_local_p) (node->decl)
++ else if ((DECL_WEAK (node->decl) || !(*targetm.binds_local_p) (node->decl))
+ && !DECL_COMDAT (node->decl) && !DECL_EXTERNAL (node->decl))
+ avail = AVAIL_OVERWRITABLE;
+ else avail = AVAIL_AVAILABLE;
+@@ -1190,7 +1190,8 @@ cgraph_variable_initializer_availability (struct cgraph_varpool_node *node)
+ /* If the variable can be overwritten, return OVERWRITABLE. Takes
+ care of at least two notable extensions - the COMDAT variables
+ used to share template instantiations in C++. */
+- if (!(*targetm.binds_local_p) (node->decl) && !DECL_COMDAT (node->decl))
++ if ((DECL_WEAK (node->decl) || !(*targetm.binds_local_p) (node->decl))
++ && !DECL_COMDAT (node->decl))
+ return AVAIL_OVERWRITABLE;
+ return AVAIL_AVAILABLE;
+ }
+diff --git a/gcc/ipa-inline.c b/gcc/ipa-inline.c
+index 84ef830..73d9fcc 100644
+--- a/gcc/ipa-inline.c
++++ b/gcc/ipa-inline.c
+@@ -300,7 +300,7 @@ cgraph_default_inline_p (struct cgraph_node *n, const char **reason)
+
+ if (n->inline_decl)
+ decl = n->inline_decl;
+- if (!DECL_INLINE (decl))
++ if (!DECL_INLINE (decl) || DECL_WEAK (decl))
+ {
+ if (reason)
+ *reason = N_("function not inlinable");
+diff --git a/gcc/ipa-pure-const.c b/gcc/ipa-pure-const.c
+index fdaff50..1bfd577 100644
+--- a/gcc/ipa-pure-const.c
++++ b/gcc/ipa-pure-const.c
+@@ -512,7 +512,7 @@ analyze_function (struct cgraph_node *fn)
+ /* If this function does not return normally or does not bind local,
+ do not touch this unless it has been marked as const or pure by the
+ front end. */
+- if (TREE_THIS_VOLATILE (decl)
++ if (TREE_THIS_VOLATILE (decl) || DECL_WEAK (decl)
+ || !targetm.binds_local_p (decl))
+ {
+ l->pure_const_state = IPA_NEITHER;
+diff --git a/gcc/tree-inline.c b/gcc/tree-inline.c
+index 1c0b79b..5a3ba7e 100644
+--- a/gcc/tree-inline.c
++++ b/gcc/tree-inline.c
+@@ -1522,6 +1522,8 @@ inlinable_function_p (tree fn)
+ else if (!DECL_INLINE (fn) && !flag_unit_at_a_time)
+ inlinable = false;
+
++ else if (DECL_WEAK (fn))
++ inlinable = false;
+ else if (inline_forbidden_p (fn))
+ {
+ /* See if we should warn about uninlinable functions. Previously,
--- /dev/null
+diff --git a/config.sub b/config.sub
+index b83660a..b81ad9a 100755
+--- a/config.sub
++++ b/config.sub
+@@ -277,7 +277,7 @@ case $basic_machine in
+ | powerpc | powerpc64 | powerpc64le | powerpcle | ppcbe \
+ | pyramid \
+ | score \
+- | sh | sh[1234] | sh[24]a | sh[23]e | sh[34]eb | sheb | shbe | shle | sh[1234]le | sh3ele \
++ | sh | sh[1234] | sh[24]a | sh[23]e | sh[1234]eb | sheb | shbe | shle | sh[1234]le | sh3ele \
+ | sh64 | sh64le \
+ | sparc | sparc64 | sparc64b | sparc64v | sparc86x | sparclet | sparclite \
+ | sparcv8 | sparcv9 | sparcv9b | sparcv9v \
+@@ -358,7 +358,7 @@ case $basic_machine in
+ | powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* | ppcbe-* \
+ | pyramid-* \
+ | romp-* | rs6000-* \
+- | sh-* | sh[1234]-* | sh[24]a-* | sh[23]e-* | sh[34]eb-* | sheb-* | shbe-* \
++ | sh-* | sh[1234]-* | sh[24]a-* | sh[23]e-* | sh[1234]eb-* | sheb-* | shbe-* \
+ | shle-* | sh[1234]le-* | sh3ele-* | sh64-* | sh64le-* \
+ | sparc-* | sparc64-* | sparc64b-* | sparc64v-* | sparc86x-* | sparclet-* \
+ | sparclite-* \
+@@ -1127,7 +1127,7 @@ case $basic_machine in
+ we32k)
+ basic_machine=we32k-att
+ ;;
+- sh[1234] | sh[24]a | sh[34]eb | sh[1234]le | sh[23]ele)
++ sh[1234] | sh[24]a | sh[1234]eb | sh[1234]le | sh[23]ele)
+ basic_machine=sh-unknown
+ ;;
+ sparc | sparcv8 | sparcv9 | sparcv9b | sparcv9v)
+diff --git a/gcc/config.gcc b/gcc/config.gcc
+index 25136b7..3779369 100644
+--- a/gcc/config.gcc
++++ b/gcc/config.gcc
+@@ -1967,7 +1967,7 @@ score-*-elf)
+ ;;
+ sh-*-elf* | sh[12346l]*-*-elf* | sh*-*-kaos* | \
+ sh-*-symbianelf* | sh[12346l]*-*-symbianelf* | \
+- sh-*-linux* | sh[346lbe]*-*-linux* | \
++ sh-*-linux* | sh[12346lbe]*-*-linux* | \
+ sh-*-netbsdelf* | shl*-*-netbsdelf* | sh5-*-netbsd* | sh5l*-*-netbsd* | \
+ sh64-*-netbsd* | sh64l*-*-netbsd*)
+ tmake_file="${tmake_file} sh/t-sh sh/t-elf"
+@@ -2911,7 +2911,7 @@ case "${target}" in
+ esac
+ ;;
+
+- sh[123456ble]-*-* | sh-*-*)
++ sh[123456ble]*-*-* | sh-*-*)
+ supported_defaults="cpu"
+ case "`echo $with_cpu | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ_ abcdefghijklmnopqrstuvwxyz- | sed s/sh/m/`" in
+ "" | m1 | m2 | m2e | m3 | m3e | m4 | m4-single | m4-single-only | m4-nofpu )
+diff --git a/gcc/configure b/gcc/configure
+index a248d39..c12f091 100755
+--- a/gcc/configure
++++ b/gcc/configure
+@@ -14564,7 +14564,7 @@ foo: .long 25
+ tls_first_minor=14
+ tls_as_opt="-m64 -Aesame --fatal-warnings"
+ ;;
+- sh-*-* | sh[34]-*-*)
++ sh-*-* | sh[123456789lbe]*-*-*)
+ conftest_s='
+ .section ".tdata","awT",@progbits
+ foo: .long 25
+diff --git a/gcc/configure.ac b/gcc/configure.ac
+index b6c394c..1414f9e 100644
+--- a/gcc/configure.ac
++++ b/gcc/configure.ac
+@@ -2538,7 +2538,7 @@ foo: .long 25
+ tls_first_minor=14
+ tls_as_opt="-m64 -Aesame --fatal-warnings"
+ ;;
+- sh-*-* | sh[34]-*-*)
++ sh-*-* | sh[123456789lbe]*-*-*)
+ conftest_s='
+ .section ".tdata","awT",@progbits
+ foo: .long 25
--- /dev/null
+diff --git a/gcc/config/linux.h b/gcc/config/linux.h
+index 1967b46..39f8cb4 100644
+--- a/gcc/config/linux.h
++++ b/gcc/config/linux.h
+@@ -41,8 +41,8 @@ Boston, MA 02110-1301, USA. */
+ #undef STARTFILE_SPEC
+ #if defined HAVE_LD_PIE
+ #define STARTFILE_SPEC \
+- "%{!shared: %{pg|p|profile:gcrt1.o%s;pie:Scrt1.o%s;:crt1.o%s}} \
+- crti.o%s %{static:crtbeginT.o%s;shared|pie:crtbeginS.o%s;:crtbegin.o%s}"
++ "%{!shared: %{pg|p|profile:gcrt1.o%s;pie:%{static:rcrt1.o%s;:Scrt1.o%s};:crt1.o%s}} \
++ crti.o%s %{shared|pie:crtbeginS.o%s;static:crtbeginT.o%s;:crtbegin.o%s}"
+ #else
+ #define STARTFILE_SPEC \
+ "%{!shared: %{pg|p|profile:gcrt1.o%s;:crt1.o%s}} \
+diff --git a/gcc/gcc.c b/gcc/gcc.c
+index 0b5ee4b..41d17a5 100644
+--- a/gcc/gcc.c
++++ b/gcc/gcc.c
+@@ -684,7 +684,7 @@ proper position among the other output files. */
+
+ #ifndef LINK_PIE_SPEC
+ #ifdef HAVE_LD_PIE
+-#define LINK_PIE_SPEC "%{pie:-pie} "
++#define LINK_PIE_SPEC "%{pie:-pie %{static:--no-dynamic-linker}} "
+ #else
+ #define LINK_PIE_SPEC "%{pie:} "
+ #endif
--- /dev/null
+diff --git a/gcc/config.gcc b/gcc/config.gcc
+index 3779369..a6d95ca 100644
+--- a/gcc/config.gcc
++++ b/gcc/config.gcc
+@@ -3101,6 +3101,12 @@ case ${target} in
+ ;;
+ esac
+
++case "x${enable_default_pie}" in
++xyes)
++ tm_defines="${tm_defines} ENABLE_DEFAULT_PIE"
++ ;;
++esac
++
+ t=
+ all_defaults="abi cpu arch tune schedule float mode fpu divide"
+ for option in $all_defaults
+diff --git a/gcc/gcc.c b/gcc/gcc.c
+index 41d17a5..b9bbcb6 100644
+--- a/gcc/gcc.c
++++ b/gcc/gcc.c
+@@ -846,8 +846,16 @@ static const char *const multilib_defaults_raw[] = MULTILIB_DEFAULTS;
+ #define GOMP_SELF_SPECS "%{fopenmp: -pthread}"
+ #endif
+
++#ifndef PIE_SELF_SPECS
++#ifdef ENABLE_DEFAULT_PIE
++#define PIE_SELF_SPECS "%{shared|pie|r|nostdlib|nopie|no-pie:;:-pie} %{fpic|fPIC|fpie|fPIE|fno-pic|fno-PIC|fno-pie|fno-PIE|D__KERNEL__:;:-fPIE}"
++#else
++#define PIE_SELF_SPECS ""
++#endif
++#endif
++
+ static const char *const driver_self_specs[] = {
+- DRIVER_SELF_SPECS, GOMP_SELF_SPECS
++ DRIVER_SELF_SPECS, GOMP_SELF_SPECS, PIE_SELF_SPECS
+ };
+
+ #ifndef OPTION_DEFAULT_SPECS
--- /dev/null
+diff --git a/Makefile.in b/Makefile.in
+index 218d8fa..45c1764 100644
+--- a/Makefile.in
++++ b/Makefile.in
+@@ -208,7 +208,7 @@ BASE_TARGET_EXPORTS = \
+ RANLIB="$(RANLIB_FOR_TARGET)"; export RANLIB; \
+ STRIP="$(STRIP_FOR_TARGET)"; export STRIP; \
+ WINDRES="$(WINDRES_FOR_TARGET)"; export WINDRES; \
+- $(RPATH_ENVVAR)=`echo "$(HOST_LIB_PATH)$(TARGET_LIB_PATH)$$$(RPATH_ENVVAR)" | sed 's,::*,:,g;s,^:*,,;s,:*$$,,'`; export $(RPATH_ENVVAR);
++ $(RPATH_ENVVAR)=`echo "$(HOST_LIB_PATH)$$$(RPATH_ENVVAR)" | sed 's,::*,:,g;s,^:*,,;s,:*$$,,'`; export $(RPATH_ENVVAR);
+
+ RAW_CXX_TARGET_EXPORTS = \
+ $(BASE_TARGET_EXPORTS) \
--- /dev/null
+diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
+index fc4e1f2..1a4cf00 100644
+--- a/gcc/config/sh/sh.h
++++ b/gcc/config/sh/sh.h
+@@ -649,10 +649,6 @@ do { \
+ /* ??? Should we use the integer SHmedia function instead? */ \
+ else if (TARGET_SHCOMPACT && TARGET_FPU_ANY) \
+ sh_div_strategy = SH_DIV_CALL_FP; \
+- /* SH1 .. SH3 cores often go into small-footprint systems, so \
+- default to the smallest implementation available. */ \
+- else if (TARGET_SH2) /* ??? EXPERIMENTAL */ \
+- sh_div_strategy = SH_DIV_CALL_TABLE; \
+ else \
+ sh_div_strategy = SH_DIV_CALL_DIV1; \
+ } \
--- /dev/null
+diff --git a/gcc/toplev.c b/gcc/toplev.c
+index 53fcdfe..85f8504 100644
+--- a/gcc/toplev.c
++++ b/gcc/toplev.c
+@@ -533,6 +533,7 @@ read_integral_parameter (const char *p, const char *pname, const int defval)
+
+ #if GCC_VERSION < 3004 || !defined (__cplusplus)
+
++#if 0
+ /* Given X, an unsigned number, return the largest int Y such that 2**Y <= X.
+ If X is 0, return -1. */
+
+@@ -582,6 +583,7 @@ exact_log2 (unsigned HOST_WIDE_INT x)
+ return floor_log2 (x);
+ #endif
+ }
++#endif
+
+ #endif /* GCC_VERSION < 3004 || !defined (__cplusplus) */
+
+diff --git a/gcc/toplev.h b/gcc/toplev.h
+index c935f7e..c8d4bb2 100644
+--- a/gcc/toplev.h
++++ b/gcc/toplev.h
+@@ -152,10 +152,10 @@ extern void decode_d_option (const char *);
+ extern bool fast_math_flags_set_p (void);
+
+ /* Return log2, or -1 if not exact. */
+-extern int exact_log2 (unsigned HOST_WIDE_INT);
++//extern int exact_log2 (unsigned HOST_WIDE_INT);
+
+ /* Return floor of log2, with -1 for zero. */
+-extern int floor_log2 (unsigned HOST_WIDE_INT);
++//extern int floor_log2 (unsigned HOST_WIDE_INT);
+
+ /* Inline versions of the above for speed. */
+ #if GCC_VERSION >= 3004
+@@ -170,13 +170,13 @@ extern int floor_log2 (unsigned HOST_WIDE_INT);
+ # define CTZ_HWI __builtin_ctz
+ # endif
+
+-extern inline int
++static inline int
+ floor_log2 (unsigned HOST_WIDE_INT x)
+ {
+ return x ? HOST_BITS_PER_WIDE_INT - 1 - (int) CLZ_HWI (x) : -1;
+ }
+
+-extern inline int
++static inline int
+ exact_log2 (unsigned HOST_WIDE_INT x)
+ {
+ return x == (x & -x) && x ? (int) CTZ_HWI (x) : -1;
--- /dev/null
+diff -ru gcc-core/gcc/config/sh/linux-unwind.h gcc-core/gcc/config/sh/linux-unwind.h
+--- gcc-core/gcc/config/sh/linux-unwind.h 2005-06-28 20:45:37.000000000 -0500
++++ gcc-core/gcc/config/sh/linux-unwind.h 2008-02-06 17:41:12.000000000 -0600
+@@ -26,6 +26,8 @@
+ the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+ Boston, MA 02110-1301, USA. */
+
++#ifndef inhibit_libc
++
+ /* Do code reading to identify a signal frame, and set the frame
+ state data appropriately. See unwind-dw2.c for the structs. */
+
+@@ -249,3 +251,5 @@
+ return _URC_NO_REASON;
+ }
+ #endif /* defined (__SH5__) */
++
++#endif
+diff -ru gcc-core/gcc/config/alpha/linux-unwind.h gcc-core2/gcc/config/alpha/linux-unwind.h
+--- gcc-core/gcc/config/alpha/linux-unwind.h 2005-06-24 20:22:41.000000000 -0500
++++ gcc-core2/gcc/config/alpha/linux-unwind.h 2010-01-10 20:05:56.000000000 -0600
+@@ -26,6 +26,8 @@
+ the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+ Boston, MA 02110-1301, USA. */
+
++#ifndef inhibit_libc
++
+ /* Do code reading to identify a signal frame, and set the frame
+ state data appropriately. See unwind-dw2.c for the structs. */
+
+@@ -80,3 +82,5 @@
+ fs->retaddr_column = 64;
+ return _URC_NO_REASON;
+ }
++
++#endif
--- /dev/null
+--- gcc-4.2.1/gcc/config/sh/sh.c.orig 2015-11-06 04:41:52.683021006 +0000
++++ gcc-4.2.1/gcc/config/sh/sh.c 2015-11-06 04:42:00.643020520 +0000
+@@ -8343,6 +8343,7 @@ nonpic_symbol_mentioned_p (rtx x)
+ || XINT (x, 1) == UNSPEC_GOTPLT
+ || XINT (x, 1) == UNSPEC_GOTTPOFF
+ || XINT (x, 1) == UNSPEC_DTPOFF
++ || XINT (x, 1) == UNSPEC_TPOFF
+ || XINT (x, 1) == UNSPEC_PLT))
+ return 0;
+
--- /dev/null
+diff --git a/fixincludes/mkfixinc.sh b/fixincludes/mkfixinc.sh
+index 6653fed..0d96c8c 100755
+--- a/fixincludes/mkfixinc.sh
++++ b/fixincludes/mkfixinc.sh
+@@ -19,7 +19,8 @@ case $machine in
+ powerpc-*-eabi* | \
+ powerpc-*-rtems* | \
+ powerpcle-*-eabisim* | \
+- powerpcle-*-eabi* )
++ powerpcle-*-eabi* | \
++ *-musl* )
+ # IF there is no include fixing,
+ # THEN create a no-op fixer and exit
+ (echo "#! /bin/sh" ; echo "exit 0" ) > ${target}
+diff --git a/gcc/config.gcc b/gcc/config.gcc
+index 3ede69b..d9eb8cf 100644
+--- a/gcc/config.gcc
++++ b/gcc/config.gcc
+@@ -575,7 +575,7 @@ case ${target} in
+ esac
+
+ # Common C libraries.
+-tm_defines="$tm_defines LIBC_GLIBC=1 LIBC_UCLIBC=2 LIBC_BIONIC=3"
++tm_defines="$tm_defines LIBC_GLIBC=1 LIBC_UCLIBC=2 LIBC_BIONIC=3 LIBC_MUSL=4"
+
+ # 32-bit x86 processors supported by --with-arch=. Each processor
+ # MUST be separated by exactly one space.
+@@ -720,6 +720,9 @@ case ${target} in
+ *-*-*uclibc*)
+ tm_defines="$tm_defines DEFAULT_LIBC=LIBC_UCLIBC"
+ ;;
++ *-*-*musl*)
++ tm_defines="$tm_defines DEFAULT_LIBC=LIBC_MUSL"
++ ;;
+ *)
+ tm_defines="$tm_defines DEFAULT_LIBC=LIBC_GLIBC"
+ ;;
+diff --git a/gcc/config/aarch64/aarch64-linux.h b/gcc/config/aarch64/aarch64-linux.h
+index ba7fc3b..1600a32 100644
+--- a/gcc/config/aarch64/aarch64-linux.h
++++ b/gcc/config/aarch64/aarch64-linux.h
+@@ -23,6 +23,9 @@
+
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"
+
++#undef MUSL_DYNAMIC_LINKER
++#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"
++
+ #undef ASAN_CC1_SPEC
+ #define ASAN_CC1_SPEC "%{%:sanitize(address):-funwind-tables}"
+
+diff --git a/gcc/config/alpha/linux.h b/gcc/config/alpha/linux.h
+index c567f43..475ea06 100644
+--- a/gcc/config/alpha/linux.h
++++ b/gcc/config/alpha/linux.h
+@@ -61,10 +61,14 @@ along with GCC; see the file COPYING3. If not see
+ #define OPTION_GLIBC (DEFAULT_LIBC == LIBC_GLIBC)
+ #define OPTION_UCLIBC (DEFAULT_LIBC == LIBC_UCLIBC)
+ #define OPTION_BIONIC (DEFAULT_LIBC == LIBC_BIONIC)
++#undef OPTION_MUSL
++#define OPTION_MUSL (DEFAULT_LIBC == LIBC_MUSL)
+ #else
+ #define OPTION_GLIBC (linux_libc == LIBC_GLIBC)
+ #define OPTION_UCLIBC (linux_libc == LIBC_UCLIBC)
+ #define OPTION_BIONIC (linux_libc == LIBC_BIONIC)
++#undef OPTION_MUSL
++#define OPTION_MUSL (linux_libc == LIBC_MUSL)
+ #endif
+
+ /* Determine what functions are present at the runtime;
+diff --git a/gcc/config/arm/linux-eabi.h b/gcc/config/arm/linux-eabi.h
+index e9d65dc..f12e6bd 100644
+--- a/gcc/config/arm/linux-eabi.h
++++ b/gcc/config/arm/linux-eabi.h
+@@ -77,6 +77,23 @@
+ %{mfloat-abi=soft*:" GLIBC_DYNAMIC_LINKER_SOFT_FLOAT "} \
+ %{!mfloat-abi=*:" GLIBC_DYNAMIC_LINKER_DEFAULT "}"
+
++/* For ARM musl currently supports four dynamic linkers:
++ - ld-musl-arm.so.1 - for the EABI-derived soft-float ABI
++ - ld-musl-armhf.so.1 - for the EABI-derived hard-float ABI
++ - ld-musl-armeb.so.1 - for the EABI-derived soft-float ABI, EB
++ - ld-musl-armebhf.so.1 - for the EABI-derived hard-float ABI, EB
++ musl does not support the legacy OABI mode.
++ All the dynamic linkers live in /lib.
++ We default to soft-float, EL. */
++#undef MUSL_DYNAMIC_LINKER
++#if TARGET_BIG_ENDIAN_DEFAULT
++#define MUSL_DYNAMIC_LINKER_E "%{mlittle-endian:;:eb}"
++#else
++#define MUSL_DYNAMIC_LINKER_E "%{mbig-endian:eb}"
++#endif
++#define MUSL_DYNAMIC_LINKER \
++ "/lib/ld-musl-arm" MUSL_DYNAMIC_LINKER_E "%{mfloat-abi=hard:hf}.so.1"
++
+ /* At this point, bpabi.h will have clobbered LINK_SPEC. We want to
+ use the GNU/Linux version, not the generic BPABI version. */
+ #undef LINK_SPEC
+diff --git a/gcc/config/glibc-stdint.h b/gcc/config/glibc-stdint.h
+index 3fc67dc..98f4f04 100644
+--- a/gcc/config/glibc-stdint.h
++++ b/gcc/config/glibc-stdint.h
+@@ -22,6 +22,12 @@ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
++/* Systems using musl libc should use this header and make sure
++ OPTION_MUSL is defined correctly before using the TYPE macros. */
++#ifndef OPTION_MUSL
++#define OPTION_MUSL 0
++#endif
++
+ #define SIG_ATOMIC_TYPE "int"
+
+ #define INT8_TYPE "signed char"
+@@ -43,12 +49,12 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ #define UINT_LEAST64_TYPE (LONG_TYPE_SIZE == 64 ? "long unsigned int" : "long long unsigned int")
+
+ #define INT_FAST8_TYPE "signed char"
+-#define INT_FAST16_TYPE (LONG_TYPE_SIZE == 64 ? "long int" : "int")
+-#define INT_FAST32_TYPE (LONG_TYPE_SIZE == 64 ? "long int" : "int")
++#define INT_FAST16_TYPE (LONG_TYPE_SIZE == 64 && !OPTION_MUSL ? "long int" : "int")
++#define INT_FAST32_TYPE (LONG_TYPE_SIZE == 64 && !OPTION_MUSL ? "long int" : "int")
+ #define INT_FAST64_TYPE (LONG_TYPE_SIZE == 64 ? "long int" : "long long int")
+ #define UINT_FAST8_TYPE "unsigned char"
+-#define UINT_FAST16_TYPE (LONG_TYPE_SIZE == 64 ? "long unsigned int" : "unsigned int")
+-#define UINT_FAST32_TYPE (LONG_TYPE_SIZE == 64 ? "long unsigned int" : "unsigned int")
++#define UINT_FAST16_TYPE (LONG_TYPE_SIZE == 64 && !OPTION_MUSL ? "long unsigned int" : "unsigned int")
++#define UINT_FAST32_TYPE (LONG_TYPE_SIZE == 64 && !OPTION_MUSL ? "long unsigned int" : "unsigned int")
+ #define UINT_FAST64_TYPE (LONG_TYPE_SIZE == 64 ? "long unsigned int" : "long long unsigned int")
+
+ #define INTPTR_TYPE (LONG_TYPE_SIZE == 64 ? "long int" : "int")
+diff --git a/gcc/config/i386/linux.h b/gcc/config/i386/linux.h
+index a100963..385aefd 100644
+--- a/gcc/config/i386/linux.h
++++ b/gcc/config/i386/linux.h
+@@ -21,3 +21,6 @@ along with GCC; see the file COPYING3. If not see
+
+ #define GNU_USER_LINK_EMULATION "elf_i386"
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
++
++#undef MUSL_DYNAMIC_LINKER
++#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-i386.so.1"
+diff --git a/gcc/config/i386/linux64.h b/gcc/config/i386/linux64.h
+index a27d3be..e300480 100644
+--- a/gcc/config/i386/linux64.h
++++ b/gcc/config/i386/linux64.h
+@@ -30,3 +30,10 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ #define GLIBC_DYNAMIC_LINKER32 "/lib/ld-linux.so.2"
+ #define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux-x86-64.so.2"
+ #define GLIBC_DYNAMIC_LINKERX32 "/libx32/ld-linux-x32.so.2"
++
++#undef MUSL_DYNAMIC_LINKER32
++#define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-i386.so.1"
++#undef MUSL_DYNAMIC_LINKER64
++#define MUSL_DYNAMIC_LINKER64 "/lib/ld-musl-x86_64.so.1"
++#undef MUSL_DYNAMIC_LINKERX32
++#define MUSL_DYNAMIC_LINKERX32 "/lib/ld-musl-x32.so.1"
+diff --git a/gcc/config/linux.h b/gcc/config/linux.h
+index 857389a..7bc87ab 100644
+--- a/gcc/config/linux.h
++++ b/gcc/config/linux.h
+@@ -32,10 +32,14 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ #define OPTION_GLIBC (DEFAULT_LIBC == LIBC_GLIBC)
+ #define OPTION_UCLIBC (DEFAULT_LIBC == LIBC_UCLIBC)
+ #define OPTION_BIONIC (DEFAULT_LIBC == LIBC_BIONIC)
++#undef OPTION_MUSL
++#define OPTION_MUSL (DEFAULT_LIBC == LIBC_MUSL)
+ #else
+ #define OPTION_GLIBC (linux_libc == LIBC_GLIBC)
+ #define OPTION_UCLIBC (linux_libc == LIBC_UCLIBC)
+ #define OPTION_BIONIC (linux_libc == LIBC_BIONIC)
++#undef OPTION_MUSL
++#define OPTION_MUSL (linux_libc == LIBC_MUSL)
+ #endif
+
+ #define GNU_USER_TARGET_OS_CPP_BUILTINS() \
+@@ -50,21 +54,25 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ } while (0)
+
+ /* Determine which dynamic linker to use depending on whether GLIBC or
+- uClibc or Bionic is the default C library and whether
+- -muclibc or -mglibc or -mbionic has been passed to change the default. */
++ uClibc or Bionic or musl is the default C library and whether
++ -muclibc or -mglibc or -mbionic or -mmusl has been passed to change
++ the default. */
+
+-#define CHOOSE_DYNAMIC_LINKER1(LIBC1, LIBC2, LIBC3, LD1, LD2, LD3) \
+- "%{" LIBC2 ":" LD2 ";:%{" LIBC3 ":" LD3 ";:" LD1 "}}"
++#define CHOOSE_DYNAMIC_LINKER1(LIBC1, LIBC2, LIBC3, LIBC4, LD1, LD2, LD3, LD4) \
++ "%{" LIBC2 ":" LD2 ";:%{" LIBC3 ":" LD3 ";:%{" LIBC4 ":" LD4 ";:" LD1 "}}}"
+
+ #if DEFAULT_LIBC == LIBC_GLIBC
+-#define CHOOSE_DYNAMIC_LINKER(G, U, B) \
+- CHOOSE_DYNAMIC_LINKER1 ("mglibc", "muclibc", "mbionic", G, U, B)
++#define CHOOSE_DYNAMIC_LINKER(G, U, B, M) \
++ CHOOSE_DYNAMIC_LINKER1 ("mglibc", "muclibc", "mbionic", "mmusl", G, U, B, M)
+ #elif DEFAULT_LIBC == LIBC_UCLIBC
+-#define CHOOSE_DYNAMIC_LINKER(G, U, B) \
+- CHOOSE_DYNAMIC_LINKER1 ("muclibc", "mglibc", "mbionic", U, G, B)
++#define CHOOSE_DYNAMIC_LINKER(G, U, B, M) \
++ CHOOSE_DYNAMIC_LINKER1 ("muclibc", "mglibc", "mbionic", "mmusl", U, G, B, M)
+ #elif DEFAULT_LIBC == LIBC_BIONIC
+-#define CHOOSE_DYNAMIC_LINKER(G, U, B) \
+- CHOOSE_DYNAMIC_LINKER1 ("mbionic", "mglibc", "muclibc", B, G, U)
++#define CHOOSE_DYNAMIC_LINKER(G, U, B, M) \
++ CHOOSE_DYNAMIC_LINKER1 ("mbionic", "mglibc", "muclibc", "mmusl", B, G, U, M)
++#elif DEFAULT_LIBC == LIBC_MUSL
++#define CHOOSE_DYNAMIC_LINKER(G, U, B, M) \
++ CHOOSE_DYNAMIC_LINKER1 ("mmusl", "mglibc", "muclibc", "mbionic", M, G, U, B)
+ #else
+ #error "Unsupported DEFAULT_LIBC"
+ #endif /* DEFAULT_LIBC */
+@@ -81,24 +89,100 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ #define BIONIC_DYNAMIC_LINKER32 "/system/bin/linker"
+ #define BIONIC_DYNAMIC_LINKER64 "/system/bin/linker64"
+ #define BIONIC_DYNAMIC_LINKERX32 "/system/bin/linkerx32"
++/* Should be redefined for each target that supports musl. */
++#define MUSL_DYNAMIC_LINKER "/dev/null"
++#define MUSL_DYNAMIC_LINKER32 "/dev/null"
++#define MUSL_DYNAMIC_LINKER64 "/dev/null"
++#define MUSL_DYNAMIC_LINKERX32 "/dev/null"
+
+ #define GNU_USER_DYNAMIC_LINKER \
+ CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER, \
+- BIONIC_DYNAMIC_LINKER)
++ BIONIC_DYNAMIC_LINKER, MUSL_DYNAMIC_LINKER)
+ #define GNU_USER_DYNAMIC_LINKER32 \
+ CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER32, UCLIBC_DYNAMIC_LINKER32, \
+- BIONIC_DYNAMIC_LINKER32)
++ BIONIC_DYNAMIC_LINKER32, MUSL_DYNAMIC_LINKER32)
+ #define GNU_USER_DYNAMIC_LINKER64 \
+ CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER64, UCLIBC_DYNAMIC_LINKER64, \
+- BIONIC_DYNAMIC_LINKER64)
++ BIONIC_DYNAMIC_LINKER64, MUSL_DYNAMIC_LINKER64)
+ #define GNU_USER_DYNAMIC_LINKERX32 \
+ CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKERX32, UCLIBC_DYNAMIC_LINKERX32, \
+- BIONIC_DYNAMIC_LINKERX32)
++ BIONIC_DYNAMIC_LINKERX32, MUSL_DYNAMIC_LINKERX32)
+
+ /* Whether we have Bionic libc runtime */
+ #undef TARGET_HAS_BIONIC
+ #define TARGET_HAS_BIONIC (OPTION_BIONIC)
+
++/* musl avoids problematic includes by rearranging the include directories.
++ * Unfortunately, this is mostly duplicated from cppdefault.c */
++#if DEFAULT_LIBC == LIBC_MUSL
++#define INCLUDE_DEFAULTS_MUSL_GPP \
++ { GPLUSPLUS_INCLUDE_DIR, "G++", 1, 1, \
++ GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 0 }, \
++ { GPLUSPLUS_TOOL_INCLUDE_DIR, "G++", 1, 1, \
++ GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 1 }, \
++ { GPLUSPLUS_BACKWARD_INCLUDE_DIR, "G++", 1, 1, \
++ GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 0 },
++
++#ifdef LOCAL_INCLUDE_DIR
++#define INCLUDE_DEFAULTS_MUSL_LOCAL \
++ { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 2 }, \
++ { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 0 },
++#else
++#define INCLUDE_DEFAULTS_MUSL_LOCAL
++#endif
++
++#ifdef PREFIX_INCLUDE_DIR
++#define INCLUDE_DEFAULTS_MUSL_PREFIX \
++ { PREFIX_INCLUDE_DIR, 0, 0, 1, 0, 0},
++#else
++#define INCLUDE_DEFAULTS_MUSL_PREFIX
++#endif
++
++#ifdef CROSS_INCLUDE_DIR
++#define INCLUDE_DEFAULTS_MUSL_CROSS \
++ { CROSS_INCLUDE_DIR, "GCC", 0, 0, 0, 0},
++#else
++#define INCLUDE_DEFAULTS_MUSL_CROSS
++#endif
++
++#ifdef TOOL_INCLUDE_DIR
++#define INCLUDE_DEFAULTS_MUSL_TOOL \
++ { TOOL_INCLUDE_DIR, "BINUTILS", 0, 1, 0, 0},
++#else
++#define INCLUDE_DEFAULTS_MUSL_TOOL
++#endif
++
++#ifdef NATIVE_SYSTEM_HEADER_DIR
++#define INCLUDE_DEFAULTS_MUSL_NATIVE \
++ { NATIVE_SYSTEM_HEADER_DIR, 0, 0, 0, 1, 2 }, \
++ { NATIVE_SYSTEM_HEADER_DIR, 0, 0, 0, 1, 0 },
++#else
++#define INCLUDE_DEFAULTS_MUSL_NATIVE
++#endif
++
++#if defined (CROSS_DIRECTORY_STRUCTURE) && !defined (TARGET_SYSTEM_ROOT)
++# undef INCLUDE_DEFAULTS_MUSL_LOCAL
++# define INCLUDE_DEFAULTS_MUSL_LOCAL
++# undef INCLUDE_DEFAULTS_MUSL_NATIVE
++# define INCLUDE_DEFAULTS_MUSL_NATIVE
++#else
++# undef INCLUDE_DEFAULTS_MUSL_CROSS
++# define INCLUDE_DEFAULTS_MUSL_CROSS
++#endif
++
++#undef INCLUDE_DEFAULTS
++#define INCLUDE_DEFAULTS \
++ { \
++ INCLUDE_DEFAULTS_MUSL_GPP \
++ INCLUDE_DEFAULTS_MUSL_PREFIX \
++ INCLUDE_DEFAULTS_MUSL_CROSS \
++ INCLUDE_DEFAULTS_MUSL_TOOL \
++ INCLUDE_DEFAULTS_MUSL_NATIVE \
++ { GCC_INCLUDE_DIR, "GCC", 0, 1, 0, 0 }, \
++ { 0, 0, 0, 0, 0, 0 } \
++ }
++#endif
++
+ #if (DEFAULT_LIBC == LIBC_UCLIBC) && defined (SINGLE_LIBC) /* uClinux */
+ /* This is a *uclinux* target. We don't define below macros to normal linux
+ versions, because doing so would require *uclinux* targets to include
+diff --git a/gcc/config/linux.opt b/gcc/config/linux.opt
+index c054338..ef055a7 100644
+--- a/gcc/config/linux.opt
++++ b/gcc/config/linux.opt
+@@ -28,5 +28,9 @@ Target Report RejectNegative Var(linux_libc,LIBC_GLIBC) Negative(muclibc)
+ Use GNU C library
+
+ muclibc
+-Target Report RejectNegative Var(linux_libc,LIBC_UCLIBC) Negative(mbionic)
++Target Report RejectNegative Var(linux_libc,LIBC_UCLIBC) Negative(mmusl)
+ Use uClibc C library
++
++mmusl
++Target Report RejectNegative Var(linux_libc,LIBC_MUSL) Negative(mbionic)
++Use musl C library
+diff --git a/gcc/config/microblaze/linux.h b/gcc/config/microblaze/linux.h
+index 655a70f..a8a3f3e 100644
+--- a/gcc/config/microblaze/linux.h
++++ b/gcc/config/microblaze/linux.h
+@@ -28,10 +28,20 @@
+ #undef TLS_NEEDS_GOT
+ #define TLS_NEEDS_GOT 1
+
+-#define DYNAMIC_LINKER "/lib/ld.so.1"
++#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
++
++#if TARGET_BIG_ENDIAN_DEFAULT == 0 /* LE */
++#define MUSL_DYNAMIC_LINKER_E "%{mbig-endian:;:el}"
++#else
++#define MUSL_DYNAMIC_LINKER_E "%{mlittle-endian:el}"
++#endif
++
++#undef MUSL_DYNAMIC_LINKER
++#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-microblaze" MUSL_DYNAMIC_LINKER_E ".so.1"
++
+ #undef SUBTARGET_EXTRA_SPECS
+ #define SUBTARGET_EXTRA_SPECS \
+- { "dynamic_linker", DYNAMIC_LINKER }
++ { "dynamic_linker", GNU_USER_DYNAMIC_LINKER }
+
+ #undef LINK_SPEC
+ #define LINK_SPEC "%{shared:-shared} \
+diff --git a/gcc/config/mips/linux.h b/gcc/config/mips/linux.h
+index 91df261..fb358e2 100644
+--- a/gcc/config/mips/linux.h
++++ b/gcc/config/mips/linux.h
+@@ -37,7 +37,13 @@ along with GCC; see the file COPYING3. If not see
+ #define UCLIBC_DYNAMIC_LINKERN32 \
+ "%{mnan=2008:/lib32/ld-uClibc-mipsn8.so.0;:/lib32/ld-uClibc.so.0}"
+
++#undef MUSL_DYNAMIC_LINKER32
++#define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-mips%{EL:el}%{msoft-float:-sf}.so.1"
++#undef MUSL_DYNAMIC_LINKER64
++#define MUSL_DYNAMIC_LINKER64 "/lib/ld-musl-mips64%{EL:el}%{msoft-float:-sf}.so.1"
++#define MUSL_DYNAMIC_LINKERN32 "/lib/ld-musl-mipsn32%{EL:el}%{msoft-float:-sf}.so.1"
++
+ #define BIONIC_DYNAMIC_LINKERN32 "/system/bin/linker32"
+ #define GNU_USER_DYNAMIC_LINKERN32 \
+ CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKERN32, UCLIBC_DYNAMIC_LINKERN32, \
+- BIONIC_DYNAMIC_LINKERN32)
++ BIONIC_DYNAMIC_LINKERN32, MUSL_DYNAMIC_LINKERN32)
+diff --git a/gcc/config/rs6000/linux.h b/gcc/config/rs6000/linux.h
+index fe0ebd6..a68ff69 100644
+--- a/gcc/config/rs6000/linux.h
++++ b/gcc/config/rs6000/linux.h
+@@ -30,10 +30,14 @@
+ #define OPTION_GLIBC (DEFAULT_LIBC == LIBC_GLIBC)
+ #define OPTION_UCLIBC (DEFAULT_LIBC == LIBC_UCLIBC)
+ #define OPTION_BIONIC (DEFAULT_LIBC == LIBC_BIONIC)
++#undef OPTION_MUSL
++#define OPTION_MUSL (DEFAULT_LIBC == LIBC_MUSL)
+ #else
+ #define OPTION_GLIBC (linux_libc == LIBC_GLIBC)
+ #define OPTION_UCLIBC (linux_libc == LIBC_UCLIBC)
+ #define OPTION_BIONIC (linux_libc == LIBC_BIONIC)
++#undef OPTION_MUSL
++#define OPTION_MUSL (linux_libc == LIBC_MUSL)
+ #endif
+
+ /* Determine what functions are present at the runtime;
+diff --git a/gcc/config/rs6000/linux64.h b/gcc/config/rs6000/linux64.h
+index 0879e7e..6a7d435 100644
+--- a/gcc/config/rs6000/linux64.h
++++ b/gcc/config/rs6000/linux64.h
+@@ -299,10 +299,14 @@ extern int dot_symbols;
+ #define OPTION_GLIBC (DEFAULT_LIBC == LIBC_GLIBC)
+ #define OPTION_UCLIBC (DEFAULT_LIBC == LIBC_UCLIBC)
+ #define OPTION_BIONIC (DEFAULT_LIBC == LIBC_BIONIC)
++#undef OPTION_MUSL
++#define OPTION_MUSL (DEFAULT_LIBC == LIBC_MUSL)
+ #else
+ #define OPTION_GLIBC (linux_libc == LIBC_GLIBC)
+ #define OPTION_UCLIBC (linux_libc == LIBC_UCLIBC)
+ #define OPTION_BIONIC (linux_libc == LIBC_BIONIC)
++#undef OPTION_MUSL
++#define OPTION_MUSL (linux_libc == LIBC_MUSL)
+ #endif
+
+ /* Determine what functions are present at the runtime;
+@@ -365,17 +369,23 @@ extern int dot_symbols;
+ #endif
+ #define UCLIBC_DYNAMIC_LINKER32 "/lib/ld-uClibc.so.0"
+ #define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0"
++#define MUSL_DYNAMIC_LINKER32 \
++ "/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1"
++#define MUSL_DYNAMIC_LINKER64 \
++ "/lib/ld-musl-powerpc64" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1"
+ #if DEFAULT_LIBC == LIBC_UCLIBC
+-#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
++#define CHOOSE_DYNAMIC_LINKER(G, U, M) "%{mglibc:" G ";:%{mmusl:" M ";:" U "}}"
+ #elif DEFAULT_LIBC == LIBC_GLIBC
+-#define CHOOSE_DYNAMIC_LINKER(G, U) "%{muclibc:" U ";:" G "}"
++#define CHOOSE_DYNAMIC_LINKER(G, U, M) "%{muclibc:" U ";:%{mmusl:" M ";:" G "}}"
++#elif DEFAULT_LIBC == LIBC_MUSL
++#define CHOOSE_DYNAMIC_LINKER(G, U, M) "%{mglibc:" G ";:%{muclibc:" U ";:" M "}}"
+ #else
+ #error "Unsupported DEFAULT_LIBC"
+ #endif
+ #define GNU_USER_DYNAMIC_LINKER32 \
+- CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER32, UCLIBC_DYNAMIC_LINKER32)
++ CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER32, UCLIBC_DYNAMIC_LINKER32, MUSL_DYNAMIC_LINKER32)
+ #define GNU_USER_DYNAMIC_LINKER64 \
+- CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER64, UCLIBC_DYNAMIC_LINKER64)
++ CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER64, UCLIBC_DYNAMIC_LINKER64, MUSL_DYNAMIC_LINKER64)
+
+ #undef DEFAULT_ASM_ENDIAN
+ #if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN)
+diff --git a/gcc/config/rs6000/secureplt.h b/gcc/config/rs6000/secureplt.h
+index b463463..77edf2a 100644
+--- a/gcc/config/rs6000/secureplt.h
++++ b/gcc/config/rs6000/secureplt.h
+@@ -18,3 +18,4 @@ along with GCC; see the file COPYING3. If not see
+ <http://www.gnu.org/licenses/>. */
+
+ #define CC1_SECURE_PLT_DEFAULT_SPEC "-msecure-plt"
++#define LINK_SECURE_PLT_DEFAULT_SPEC "--secure-plt"
+diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h
+index 9917c2f..68365de 100644
+--- a/gcc/config/rs6000/sysv4.h
++++ b/gcc/config/rs6000/sysv4.h
+@@ -537,6 +537,9 @@ ENDIAN_SELECT(" -mbig", " -mlittle", DEFAULT_ASM_ENDIAN)
+ #ifndef CC1_SECURE_PLT_DEFAULT_SPEC
+ #define CC1_SECURE_PLT_DEFAULT_SPEC ""
+ #endif
++#ifndef LINK_SECURE_PLT_DEFAULT_SPEC
++#define LINK_SECURE_PLT_DEFAULT_SPEC ""
++#endif
+
+ /* Pass -G xxx to the compiler. */
+ #undef CC1_SPEC
+@@ -586,7 +589,8 @@ ENDIAN_SELECT(" -mbig", " -mlittle", DEFAULT_ASM_ENDIAN)
+
+ /* Override the default target of the linker. */
+ #define LINK_TARGET_SPEC \
+- ENDIAN_SELECT("", " --oformat elf32-powerpcle", "")
++ ENDIAN_SELECT("", " --oformat elf32-powerpcle", "") \
++ "%{!mbss-plt: %{!msecure-plt: %(link_secure_plt_default)}}"
+
+ /* Any specific OS flags. */
+ #define LINK_OS_SPEC "\
+@@ -762,17 +766,23 @@ ENDIAN_SELECT(" -mbig", " -mlittle", DEFAULT_ASM_ENDIAN)
+
+ #define LINK_START_LINUX_SPEC ""
+
++#define MUSL_DYNAMIC_LINKER_E ENDIAN_SELECT("","le","")
++
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
+ #define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
++#define MUSL_DYNAMIC_LINKER \
++ "/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1"
+ #if DEFAULT_LIBC == LIBC_UCLIBC
+-#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
++#define CHOOSE_DYNAMIC_LINKER(G, U, M) "%{mglibc:" G ";:%{mmusl:" M ";:" U "}}"
++#elif DEFAULT_LIBC == LIBC_MUSL
++#define CHOOSE_DYNAMIC_LINKER(G, U, M) "%{mglibc:" G ";:%{muclibc:" U ";:" M "}}"
+ #elif !defined (DEFAULT_LIBC) || DEFAULT_LIBC == LIBC_GLIBC
+-#define CHOOSE_DYNAMIC_LINKER(G, U) "%{muclibc:" U ";:" G "}"
++#define CHOOSE_DYNAMIC_LINKER(G, U, M) "%{muclibc:" U ";:%{mmusl:" M ";:" G "}}"
+ #else
+ #error "Unsupported DEFAULT_LIBC"
+ #endif
+ #define GNU_USER_DYNAMIC_LINKER \
+- CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER)
++ CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER, MUSL_DYNAMIC_LINKER)
+
+ #define LINK_OS_LINUX_SPEC "-m elf32ppclinux %{!shared: %{!static: \
+ %{rdynamic:-export-dynamic} \
+@@ -895,6 +905,7 @@ ncrtn.o%s"
+ { "link_os_openbsd", LINK_OS_OPENBSD_SPEC }, \
+ { "link_os_default", LINK_OS_DEFAULT_SPEC }, \
+ { "cc1_secure_plt_default", CC1_SECURE_PLT_DEFAULT_SPEC }, \
++ { "link_secure_plt_default", LINK_SECURE_PLT_DEFAULT_SPEC }, \
+ { "cpp_os_ads", CPP_OS_ADS_SPEC }, \
+ { "cpp_os_yellowknife", CPP_OS_YELLOWKNIFE_SPEC }, \
+ { "cpp_os_mvme", CPP_OS_MVME_SPEC }, \
+@@ -949,3 +960,72 @@ ncrtn.o%s"
+ /* This target uses the sysv4.opt file. */
+ #define TARGET_USES_SYSV4_OPT 1
+
++/* Include order changes for musl, same as in generic linux.h. */
++#if DEFAULT_LIBC == LIBC_MUSL
++#define INCLUDE_DEFAULTS_MUSL_GPP \
++ { GPLUSPLUS_INCLUDE_DIR, "G++", 1, 1, \
++ GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 0 }, \
++ { GPLUSPLUS_TOOL_INCLUDE_DIR, "G++", 1, 1, \
++ GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 1 }, \
++ { GPLUSPLUS_BACKWARD_INCLUDE_DIR, "G++", 1, 1, \
++ GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 0 },
++
++#ifdef LOCAL_INCLUDE_DIR
++#define INCLUDE_DEFAULTS_MUSL_LOCAL \
++ { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 2 }, \
++ { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 0 },
++#else
++#define INCLUDE_DEFAULTS_MUSL_LOCAL
++#endif
++
++#ifdef PREFIX_INCLUDE_DIR
++#define INCLUDE_DEFAULTS_MUSL_PREFIX \
++ { PREFIX_INCLUDE_DIR, 0, 0, 1, 0, 0},
++#else
++#define INCLUDE_DEFAULTS_MUSL_PREFIX
++#endif
++
++#ifdef CROSS_INCLUDE_DIR
++#define INCLUDE_DEFAULTS_MUSL_CROSS \
++ { CROSS_INCLUDE_DIR, "GCC", 0, 0, 0, 0},
++#else
++#define INCLUDE_DEFAULTS_MUSL_CROSS
++#endif
++
++#ifdef TOOL_INCLUDE_DIR
++#define INCLUDE_DEFAULTS_MUSL_TOOL \
++ { TOOL_INCLUDE_DIR, "BINUTILS", 0, 1, 0, 0},
++#else
++#define INCLUDE_DEFAULTS_MUSL_TOOL
++#endif
++
++#ifdef NATIVE_SYSTEM_HEADER_DIR
++#define INCLUDE_DEFAULTS_MUSL_NATIVE \
++ { NATIVE_SYSTEM_HEADER_DIR, 0, 0, 0, 1, 2 }, \
++ { NATIVE_SYSTEM_HEADER_DIR, 0, 0, 0, 1, 0 },
++#else
++#define INCLUDE_DEFAULTS_MUSL_NATIVE
++#endif
++
++#if defined (CROSS_DIRECTORY_STRUCTURE) && !defined (TARGET_SYSTEM_ROOT)
++# undef INCLUDE_DEFAULTS_MUSL_LOCAL
++# define INCLUDE_DEFAULTS_MUSL_LOCAL
++# undef INCLUDE_DEFAULTS_MUSL_NATIVE
++# define INCLUDE_DEFAULTS_MUSL_NATIVE
++#else
++# undef INCLUDE_DEFAULTS_MUSL_CROSS
++# define INCLUDE_DEFAULTS_MUSL_CROSS
++#endif
++
++#undef INCLUDE_DEFAULTS
++#define INCLUDE_DEFAULTS \
++ { \
++ INCLUDE_DEFAULTS_MUSL_GPP \
++ INCLUDE_DEFAULTS_MUSL_PREFIX \
++ INCLUDE_DEFAULTS_MUSL_CROSS \
++ INCLUDE_DEFAULTS_MUSL_TOOL \
++ INCLUDE_DEFAULTS_MUSL_NATIVE \
++ { GCC_INCLUDE_DIR, "GCC", 0, 1, 0, 0 }, \
++ { 0, 0, 0, 0, 0, 0 } \
++ }
++#endif
+diff --git a/gcc/config/rs6000/sysv4le.h b/gcc/config/rs6000/sysv4le.h
+index 7b1d6a1..064323c 100644
+--- a/gcc/config/rs6000/sysv4le.h
++++ b/gcc/config/rs6000/sysv4le.h
+@@ -35,3 +35,5 @@
+ /* Little-endian PowerPC64 Linux uses the ELF v2 ABI by default. */
+ #define LINUX64_DEFAULT_ABI_ELFv2
+
++#undef MUSL_DYNAMIC_LINKER_E
++#define MUSL_DYNAMIC_LINKER_E ENDIAN_SELECT("","le","le")
+diff --git a/gcc/config/sh/linux.h b/gcc/config/sh/linux.h
+index 0f5d614..4c167c6 100644
+--- a/gcc/config/sh/linux.h
++++ b/gcc/config/sh/linux.h
+@@ -43,6 +43,29 @@ along with GCC; see the file COPYING3. If not see
+
+ #define TARGET_ASM_FILE_END file_end_indicate_exec_stack
+
++#if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
++#define MUSL_DYNAMIC_LINKER_E "%{mb:eb}"
++#else
++#define MUSL_DYNAMIC_LINKER_E "%{!ml:eb}"
++#endif
++
++#if TARGET_CPU_DEFAULT & ( MASK_HARD_SH2A_DOUBLE | MASK_SH4 )
++/* "-nofpu" if any nofpu option is specified */
++#define MUSL_DYNAMIC_LINKER_FP \
++ "%{m1|m2|m2a-nofpu|m3|m4-nofpu|m4-100-nofpu|m4-200-nofpu|m4-300-nofpu|" \
++ "m4-340|m4-400|m4-500|m4al|m5-32media-nofpu|m5-64media-nofpu|" \
++ "m5-compact-nofpu:-nofpu}"
++#else
++/* "-nofpu" if none of the hard fpu options are specified */
++#define MUSL_DYNAMIC_LINKER_FP \
++ "%{m2a|m4|m4-100|m4-200|m4-300|m4a|m5-32media|m5-64media|m5-compact:;:-nofpu}"
++#endif
++
++#undef MUSL_DYNAMIC_LINKER
++#define MUSL_DYNAMIC_LINKER \
++ "/lib/ld-musl-sh" MUSL_DYNAMIC_LINKER_E MUSL_DYNAMIC_LINKER_FP \
++ "%{mfdpic:-fdpic}.so.1"
++
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
+
+ #undef SUBTARGET_LINK_EMUL_SUFFIX
+diff --git a/gcc/configure b/gcc/configure
+index 0037240..66aab9f 100755
+--- a/gcc/configure
++++ b/gcc/configure
+@@ -27742,6 +27742,9 @@ if test "${gcc_cv_libc_provides_ssp+set}" = set; then :
+ else
+ gcc_cv_libc_provides_ssp=no
+ case "$target" in
++ *-*-musl*)
++ # All versions of musl provide stack protector
++ gcc_cv_libc_provides_ssp=yes;;
+ *-*-linux* | *-*-kfreebsd*-gnu | *-*-knetbsd*-gnu)
+ # glibc 2.4 and later provides __stack_chk_fail and
+ # either __stack_chk_guard, or TLS access to stack guard canary.
+@@ -27774,6 +27777,7 @@ fi
+ # <http://gcc.gnu.org/ml/gcc/2008-10/msg00130.html>) and for now
+ # simply assert that glibc does provide this, which is true for all
+ # realistically usable GNU/Hurd configurations.
++ # All supported versions of musl provide it as well
+ gcc_cv_libc_provides_ssp=yes;;
+ *-*-darwin* | *-*-freebsd*)
+ ac_fn_c_check_func "$LINENO" "__stack_chk_fail" "ac_cv_func___stack_chk_fail"
+@@ -27870,6 +27874,9 @@ case "$target" in
+ gcc_cv_target_dl_iterate_phdr=no
+ fi
+ ;;
++ *-linux-musl*)
++ gcc_cv_target_dl_iterate_phdr=yes
++ ;;
+ esac
+
+ if test x$gcc_cv_target_dl_iterate_phdr = xyes; then
+diff --git a/gcc/configure.ac b/gcc/configure.ac
+index 6f38ba1..b81960c 100644
+--- a/gcc/configure.ac
++++ b/gcc/configure.ac
+@@ -5229,6 +5229,9 @@ AC_CACHE_CHECK(__stack_chk_fail in target C library,
+ gcc_cv_libc_provides_ssp,
+ [gcc_cv_libc_provides_ssp=no
+ case "$target" in
++ *-*-musl*)
++ # All versions of musl provide stack protector
++ gcc_cv_libc_provides_ssp=yes;;
+ *-*-linux* | *-*-kfreebsd*-gnu | *-*-knetbsd*-gnu)
+ # glibc 2.4 and later provides __stack_chk_fail and
+ # either __stack_chk_guard, or TLS access to stack guard canary.
+@@ -5255,6 +5258,7 @@ AC_CACHE_CHECK(__stack_chk_fail in target C library,
+ # <http://gcc.gnu.org/ml/gcc/2008-10/msg00130.html>) and for now
+ # simply assert that glibc does provide this, which is true for all
+ # realistically usable GNU/Hurd configurations.
++ # All supported versions of musl provide it as well
+ gcc_cv_libc_provides_ssp=yes;;
+ *-*-darwin* | *-*-freebsd*)
+ AC_CHECK_FUNC(__stack_chk_fail,[gcc_cv_libc_provides_ssp=yes],
+@@ -5328,6 +5332,9 @@ case "$target" in
+ gcc_cv_target_dl_iterate_phdr=no
+ fi
+ ;;
++ *-linux-musl*)
++ gcc_cv_target_dl_iterate_phdr=yes
++ ;;
+ esac
+ GCC_TARGET_TEMPLATE([TARGET_DL_ITERATE_PHDR])
+ if test x$gcc_cv_target_dl_iterate_phdr = xyes; then
+diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
+index f84a199..ee9765b 100644
+--- a/gcc/doc/invoke.texi
++++ b/gcc/doc/invoke.texi
+@@ -667,7 +667,7 @@ Objective-C and Objective-C++ Dialects}.
+ -mcpu=@var{cpu}}
+
+ @emph{GNU/Linux Options}
+-@gccoptlist{-mglibc -muclibc -mbionic -mandroid @gol
++@gccoptlist{-mglibc -muclibc -mmusl -mbionic -mandroid @gol
+ -tno-android-cc -tno-android-ld}
+
+ @emph{H8/300 Options}
+@@ -15324,13 +15324,19 @@ These @samp{-m} options are defined for GNU/Linux targets:
+ @item -mglibc
+ @opindex mglibc
+ Use the GNU C library. This is the default except
+-on @samp{*-*-linux-*uclibc*} and @samp{*-*-linux-*android*} targets.
++on @samp{*-*-linux-*uclibc*}, @samp{*-*-linux-*musl*} and
++@samp{*-*-linux-*android*} targets.
+
+ @item -muclibc
+ @opindex muclibc
+ Use uClibc C library. This is the default on
+ @samp{*-*-linux-*uclibc*} targets.
+
++@item -mmusl
++@opindex mmusl
++Use the musl C library. This is the default on
++@samp{*-*-linux-*musl*} targets.
++
+ @item -mbionic
+ @opindex mbionic
+ Use Bionic C library. This is the default on
+diff --git a/libcilkrts/runtime/os-unix.c b/libcilkrts/runtime/os-unix.c
+index cb582dd..e43d7d5 100644
+--- a/libcilkrts/runtime/os-unix.c
++++ b/libcilkrts/runtime/os-unix.c
+@@ -51,6 +51,7 @@
+ #if defined __linux__
+ # include <sys/sysinfo.h>
+ # include <sys/syscall.h>
++# include <sched.h>
+ #elif defined __APPLE__
+ # include <sys/sysctl.h>
+ // Uses sysconf(_SC_NPROCESSORS_ONLN) in verbose output
+@@ -400,28 +401,19 @@ COMMON_SYSDEP void __cilkrts_sleep(void)
+
+ COMMON_SYSDEP void __cilkrts_yield(void)
+ {
+-#if __APPLE__ || __FreeBSD__ || __VXWORKS__
+- // On MacOS, call sched_yield to yield quantum. I'm not sure why we
+- // don't do this on Linux also.
+- sched_yield();
+-#elif defined(__DragonFly__)
+- // On DragonFly BSD, call sched_yield to yield quantum.
+- sched_yield();
+-#elif defined(__MIC__)
++#if defined(__MIC__)
+ // On MIC, pthread_yield() really trashes things. Arch's measurements
+ // showed that calling _mm_delay_32() (or doing nothing) was a better
+ // option. Delaying 1024 clock cycles is a reasonable compromise between
+ // giving up the processor and latency starting up when work becomes
+ // available
+ _mm_delay_32(1024);
+-#elif defined(__ANDROID__) || (defined(__sun__) && defined(__svr4__))
+- // On Android and Solaris, call sched_yield to yield quantum. I'm not
+- // sure why we don't do this on Linux also.
+- sched_yield();
+-#else
+- // On Linux, call pthread_yield (which in turn will call sched_yield)
+- // to yield quantum.
++#elif defined(__sun__) && !defined(__svr4__)
++ // On old SunOS call pthread_yield to yield a quantum.
+ pthread_yield();
++#else
++ // On other platforms call sched_yield to yield a quantum.
++ sched_yield();
+ #endif
+ }
+
+diff --git a/libgcc/unwind-dw2-fde-dip.c b/libgcc/unwind-dw2-fde-dip.c
+index e1e566b..137dced 100644
+--- a/libgcc/unwind-dw2-fde-dip.c
++++ b/libgcc/unwind-dw2-fde-dip.c
+@@ -59,6 +59,12 @@
+
+ #if !defined(inhibit_libc) && defined(HAVE_LD_EH_FRAME_HDR) \
+ && defined(TARGET_DL_ITERATE_PHDR) \
++ && defined(__linux__)
++# define USE_PT_GNU_EH_FRAME
++#endif
++
++#if !defined(inhibit_libc) && defined(HAVE_LD_EH_FRAME_HDR) \
++ && defined(TARGET_DL_ITERATE_PHDR) \
+ && (defined(__DragonFly__) || defined(__FreeBSD__))
+ # define ElfW __ElfN
+ # define USE_PT_GNU_EH_FRAME
+diff --git a/libgfortran/acinclude.m4 b/libgfortran/acinclude.m4
+index ba890f9..30b8b1a6 100644
+--- a/libgfortran/acinclude.m4
++++ b/libgfortran/acinclude.m4
+@@ -100,7 +100,7 @@ void foo (void);
+ [Define to 1 if the target supports #pragma weak])
+ fi
+ case "$host" in
+- *-*-darwin* | *-*-hpux* | *-*-cygwin* | *-*-mingw* )
++ *-*-darwin* | *-*-hpux* | *-*-cygwin* | *-*-mingw* | *-*-musl* )
+ AC_DEFINE(GTHREAD_USE_WEAK, 0,
+ [Define to 0 if the target shouldn't use #pragma weak])
+ ;;
+diff --git a/libgfortran/configure b/libgfortran/configure
+index e1592f7..07542e1 100755
+--- a/libgfortran/configure
++++ b/libgfortran/configure
+@@ -26447,7 +26447,7 @@ $as_echo "#define SUPPORTS_WEAK 1" >>confdefs.h
+
+ fi
+ case "$host" in
+- *-*-darwin* | *-*-hpux* | *-*-cygwin* | *-*-mingw* )
++ *-*-darwin* | *-*-hpux* | *-*-cygwin* | *-*-mingw* | *-*-musl* )
+
+ $as_echo "#define GTHREAD_USE_WEAK 0" >>confdefs.h
+
+diff --git a/libitm/config/arm/hwcap.cc b/libitm/config/arm/hwcap.cc
+index a1c2cfd..ea8f023 100644
+--- a/libitm/config/arm/hwcap.cc
++++ b/libitm/config/arm/hwcap.cc
+@@ -40,7 +40,7 @@ int GTM_hwcap HIDDEN = 0
+
+ #ifdef __linux__
+ #include <unistd.h>
+-#include <sys/fcntl.h>
++#include <fcntl.h>
+ #include <elf.h>
+
+ static void __attribute__((constructor))
+diff --git a/libitm/config/linux/x86/tls.h b/libitm/config/linux/x86/tls.h
+index e731ab7..54ad8b6 100644
+--- a/libitm/config/linux/x86/tls.h
++++ b/libitm/config/linux/x86/tls.h
+@@ -25,16 +25,19 @@
+ #ifndef LIBITM_X86_TLS_H
+ #define LIBITM_X86_TLS_H 1
+
+-#if defined(__GLIBC_PREREQ) && __GLIBC_PREREQ(2, 10)
++#if defined(__GLIBC_PREREQ)
++#if __GLIBC_PREREQ(2, 10)
+ /* Use slots in the TCB head rather than __thread lookups.
+ GLIBC has reserved words 10 through 13 for TM. */
+ #define HAVE_ARCH_GTM_THREAD 1
+ #define HAVE_ARCH_GTM_THREAD_DISP 1
+ #endif
++#endif
+
+ #include "config/generic/tls.h"
+
+-#if defined(__GLIBC_PREREQ) && __GLIBC_PREREQ(2, 10)
++#if defined(__GLIBC_PREREQ)
++#if __GLIBC_PREREQ(2, 10)
+ namespace GTM HIDDEN {
+
+ #ifdef __x86_64__
+@@ -101,5 +104,6 @@ static inline void set_abi_disp(struct abi_dispatch *x)
+
+ } // namespace GTM
+ #endif /* >= GLIBC 2.10 */
++#endif
+
+ #endif // LIBITM_X86_TLS_H
+diff --git a/libstdc++-v3/config/os/generic/os_defines.h b/libstdc++-v3/config/os/generic/os_defines.h
+index 45bf52a..103ec0e 100644
+--- a/libstdc++-v3/config/os/generic/os_defines.h
++++ b/libstdc++-v3/config/os/generic/os_defines.h
+@@ -33,4 +33,9 @@
+ // System-specific #define, typedefs, corrections, etc, go here. This
+ // file will come before all others.
+
++// Disable the weak reference logic in gthr.h for os/generic because it
++// is broken on every platform unless there is implementation specific
++// workaround in gthr-posix.h and at link-time for static linking.
++#define _GLIBCXX_GTHREAD_USE_WEAK 0
++
+ #endif
+diff --git a/libstdc++-v3/configure.host b/libstdc++-v3/configure.host
+index 640199c..106134e 100644
+--- a/libstdc++-v3/configure.host
++++ b/libstdc++-v3/configure.host
+@@ -273,6 +273,9 @@ case "${host_os}" in
+ freebsd*)
+ os_include_dir="os/bsd/freebsd"
+ ;;
++ linux-musl*)
++ os_include_dir="os/generic"
++ ;;
+ gnu* | linux* | kfreebsd*-gnu | knetbsd*-gnu)
+ if [ "$uclibc" = "yes" ]; then
+ os_include_dir="os/uclibc"
--- /dev/null
+--- a/gcc/config/sh/sh-protos.h
++++ a/gcc/config/sh/sh-protos.h
+@@ -159,6 +159,7 @@ extern int sh_eval_treg_value (rtx op);
+ extern HOST_WIDE_INT sh_disp_addr_displacement (rtx mem_op);
+ extern int sh_max_mov_insn_displacement (machine_mode mode, bool consider_sh2a);
+ extern bool sh_movsf_ie_ra_split_p (rtx, rtx, rtx);
++extern void sh_expand_sym_label2reg (rtx, rtx, rtx, bool);
+
+ /* Result value of sh_find_set_of_reg. */
+ struct set_of_reg
+--- a/gcc/config/sh/sh.c
++++ a/gcc/config/sh/sh.c
+@@ -1604,6 +1604,10 @@ sh_asm_output_addr_const_extra (FILE *file, rtx x)
+ output_addr_const (file, XVECEXP (x, 0, 0));
+ fputs ("@GOTPLT", file);
+ break;
++ case UNSPEC_PCREL:
++ output_addr_const (file, XVECEXP (x, 0, 0));
++ fputs ("@PCREL", file);
++ break;
+ case UNSPEC_DTPOFF:
+ output_addr_const (file, XVECEXP (x, 0, 0));
+ fputs ("@DTPOFF", file);
+@@ -10441,6 +10445,7 @@ nonpic_symbol_mentioned_p (rtx x)
+ || XINT (x, 1) == UNSPEC_DTPOFF
+ || XINT (x, 1) == UNSPEC_TPOFF
+ || XINT (x, 1) == UNSPEC_PLT
++ || XINT (x, 1) == UNSPEC_PCREL
+ || XINT (x, 1) == UNSPEC_SYMOFF
+ || XINT (x, 1) == UNSPEC_PCREL_SYMOFF))
+ return false;
+@@ -10714,7 +10719,8 @@ sh_delegitimize_address (rtx orig_x)
+ rtx symplt = XEXP (XVECEXP (y, 0, 0), 0);
+
+ if (GET_CODE (symplt) == UNSPEC
+- && XINT (symplt, 1) == UNSPEC_PLT)
++ && (XINT (symplt, 1) == UNSPEC_PLT
++ || XINT (symplt, 1) == UNSPEC_PCREL))
+ return XVECEXP (symplt, 0, 0);
+ }
+ }
+@@ -11702,9 +11708,24 @@ sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
+ || crtl->args.info.stack_regs == 0)
+ && ! sh_cfun_interrupt_handler_p ()
+ && (! flag_pic
+- || (decl && ! TREE_PUBLIC (decl))
++ || (decl && ! (TREE_PUBLIC (decl) || DECL_WEAK (decl)))
+ || (decl && DECL_VISIBILITY (decl) != VISIBILITY_DEFAULT)));
+ }
++
++/* Expand to appropriate sym*_label2reg for SYM and SIBCALL_P. */
++void
++sh_expand_sym_label2reg (rtx reg, rtx sym, rtx lab, bool sibcall_p)
++{
++ const_tree decl = SYMBOL_REF_DECL (sym);
++ bool is_weak = (decl && DECL_P (decl) && DECL_WEAK (decl));
++
++ if (!is_weak && SYMBOL_REF_LOCAL_P (sym))
++ emit_insn (gen_sym_label2reg (reg, sym, lab));
++ else if (sibcall_p)
++ emit_insn (gen_symPCREL_label2reg (reg, sym, lab));
++ else
++ emit_insn (gen_symPLT_label2reg (reg, sym, lab));
++}
+ \f
+ /* Machine specific built-in functions. */
+
+--- a/gcc/config/sh/sh.md
++++ a/gcc/config/sh/sh.md
+@@ -135,6 +135,7 @@
+ UNSPEC_PLT
+ UNSPEC_CALLER
+ UNSPEC_GOTPLT
++ UNSPEC_PCREL
+ UNSPEC_ICACHE
+ UNSPEC_INIT_TRAMP
+ UNSPEC_FCOSA
+@@ -9470,11 +9471,8 @@ label:
+ [(const_int 0)]
+ {
+ rtx lab = PATTERN (gen_call_site ());
+-
+- if (SYMBOL_REF_LOCAL_P (operands[0]))
+- emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
+- else
+- emit_insn (gen_symPLT_label2reg (operands[2], operands[0], lab));
++
++ sh_expand_sym_label2reg (operands[2], operands[0], lab, false);
+ emit_call_insn (gen_calli_pcrel (operands[2], operands[1], copy_rtx (lab)));
+ DONE;
+ }
+@@ -9605,10 +9603,7 @@ label:
+ {
+ rtx lab = PATTERN (gen_call_site ());
+
+- if (SYMBOL_REF_LOCAL_P (operands[1]))
+- emit_insn (gen_sym_label2reg (operands[3], operands[1], lab));
+- else
+- emit_insn (gen_symPLT_label2reg (operands[3], operands[1], lab));
++ sh_expand_sym_label2reg (operands[3], operands[1], lab, false);
+ emit_call_insn (gen_call_valuei_pcrel (operands[0], operands[3],
+ operands[2], copy_rtx (lab)));
+ DONE;
+@@ -10008,7 +10003,7 @@ label:
+ rtx lab = PATTERN (gen_call_site ());
+ rtx call_insn;
+
+- emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
++ sh_expand_sym_label2reg (operands[2], operands[0], lab, true);
+ call_insn = emit_call_insn (gen_sibcalli_pcrel (operands[2], operands[1],
+ copy_rtx (lab)));
+ SIBLING_CALL_P (call_insn) = 1;
+@@ -10200,7 +10195,7 @@ label:
+ rtx lab = PATTERN (gen_call_site ());
+ rtx call_insn;
+
+- emit_insn (gen_sym_label2reg (operands[3], operands[1], lab));
++ sh_expand_sym_label2reg (operands[3], operands[1], lab, true);
+ call_insn = emit_call_insn (gen_sibcall_valuei_pcrel (operands[0],
+ operands[3],
+ operands[2],
+@@ -10748,6 +10743,16 @@ label:
+ UNSPEC_SYMOFF)))]
+ "TARGET_SH1" "")
+
++(define_expand "symPCREL_label2reg"
++ [(set (match_operand:SI 0 "" "")
++ (const:SI
++ (unspec:SI
++ [(const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PCREL))
++ (const:SI (plus:SI (match_operand:SI 2 "" "")
++ (const_int 2)))] UNSPEC_PCREL_SYMOFF)))]
++ "TARGET_SH1"
++ "")
++
+ (define_expand "symGOT_load"
+ [(set (match_dup 2) (match_operand 1 "" ""))
+ (set (match_dup 3) (plus (match_dup 2) (reg PIC_REG)))
--- /dev/null
+--- gcc-5.2.0.orig/gcc/config.gcc
++++ gcc-5.2.0/gcc/config.gcc
+@@ -4096,7 +4099,7 @@
+ esac
+ ;;
+
+- sh[123456ble]-*-* | sh-*-*)
++ sh[123456ble]*-*-* | sh-*-*)
+ supported_defaults="cpu"
+ case "`echo $with_cpu | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ_ abcdefghijklmnopqrstuvwxyz- | sed s/sh/m/`" in
+ "" | m1 | m2 | m2e | m3 | m3e | m4 | m4-single | m4-single-only | m4-nofpu )
+--- gcc-5.2.0.base/gcc/configure.ac 2015-08-11 16:23:36.000000000 +0000
++++ gcc-5.2.0/gcc/configure.ac 2015-09-13 08:17:31.714972082 +0000
+@@ -3300,7 +3300,7 @@
+ tls_first_minor=14
+ tls_as_opt="-m64 -Aesame --fatal-warnings"
+ ;;
+- sh-*-* | sh[34]-*-*)
++ sh-*-* | sh[123456789lbe]*-*-*)
+ conftest_s='
+ .section ".tdata","awT",@progbits
+ foo: .long 25
+--- gcc-5.2.0.base/gcc/configure 2015-08-11 16:23:35.000000000 +0000
++++ gcc-5.2.0/gcc/configure 2015-09-13 08:17:42.608304751 +0000
+@@ -23754,7 +23754,7 @@
+ tls_first_minor=14
+ tls_as_opt="-m64 -Aesame --fatal-warnings"
+ ;;
+- sh-*-* | sh[34]-*-*)
++ sh-*-* | sh[123456789lbe]*-*-*)
+ conftest_s='
+ .section ".tdata","awT",@progbits
+ foo: .long 25
--- /dev/null
+diff --git a/gcc/config.gcc b/gcc/config.gcc
+index 0f2dc32..a3d0d45 100644
+--- a/gcc/config.gcc
++++ b/gcc/config.gcc
+@@ -467,7 +467,7 @@ s390*-*-*)
+ extra_headers="s390intrin.h htmintrin.h htmxlintrin.h vecintrin.h"
+ ;;
+ # Note the 'l'; we need to be able to match e.g. "shle" or "shl".
+-sh[123456789lbe]*-*-* | sh-*-*)
++sh[123456789lbej]*-*-* | sh-*-*)
+ cpu_type=sh
+ extra_options="${extra_options} fused-madd.opt"
+ extra_objs="${extra_objs} sh_treg_combine.o sh-mem.o sh_optimize_sett_clrt.o"
+@@ -2601,19 +2601,19 @@ s390x-ibm-tpf*)
+ extra_options="${extra_options} s390/tpf.opt"
+ tmake_file="${tmake_file} s390/t-s390"
+ ;;
+-sh-*-elf* | sh[12346l]*-*-elf* | \
+- sh-*-linux* | sh[2346lbe]*-*-linux* | \
++sh-*-elf* | sh[12346lj]*-*-elf* | \
++ sh-*-linux* | sh[2346lbej]*-*-linux* | \
+ sh-*-netbsdelf* | shl*-*-netbsdelf* | sh5-*-netbsd* | sh5l*-*-netbsd* | \
+ sh64-*-netbsd* | sh64l*-*-netbsd*)
+ tmake_file="${tmake_file} sh/t-sh sh/t-elf"
+ if test x${with_endian} = x; then
+ case ${target} in
+- sh[1234]*be-*-* | sh[1234]*eb-*-*) with_endian=big ;;
++ sh[j1234]*be-*-* | sh[j1234]*eb-*-*) with_endian=big ;;
+ shbe-*-* | sheb-*-*) with_endian=big,little ;;
+ sh[1234]l* | sh[34]*-*-linux*) with_endian=little ;;
+ shl* | sh64l* | sh*-*-linux* | \
+ sh5l* | sh-superh-elf) with_endian=little,big ;;
+- sh[1234]*-*-*) with_endian=big ;;
++ sh[j1234]*-*-*) with_endian=big ;;
+ *) with_endian=big,little ;;
+ esac
+ fi
+@@ -2703,6 +2703,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
+ sh2a_nofpu*) sh_cpu_target=sh2a-nofpu ;;
+ sh2a*) sh_cpu_target=sh2a ;;
+ sh2e*) sh_cpu_target=sh2e ;;
++ shj2*) sh_cpu_target=shj2;;
+ sh2*) sh_cpu_target=sh2 ;;
+ *) sh_cpu_target=sh1 ;;
+ esac
+@@ -2727,7 +2728,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
+ sh2a-single-only | sh2a-single | sh2a-nofpu | sh2a | \
+ sh4a-single-only | sh4a-single | sh4a-nofpu | sh4a | sh4al | \
+ sh4-single-only | sh4-single | sh4-nofpu | sh4 | sh4-300 | \
+- sh3e | sh3 | sh2e | sh2 | sh1) ;;
++ sh3e | sh3 | sh2e | sh2 | sh1 | shj2) ;;
+ "") sh_cpu_default=${sh_cpu_target} ;;
+ *) echo "with_cpu=$with_cpu not supported"; exit 1 ;;
+ esac
+@@ -2738,9 +2739,9 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
+ sh[1234]*) sh_multilibs=${sh_cpu_target} ;;
+ sh64* | sh5*) sh_multilibs=m5-32media,m5-32media-nofpu,m5-compact,m5-compact-nofpu,m5-64media,m5-64media-nofpu ;;
+ sh-superh-*) sh_multilibs=m4,m4-single,m4-single-only,m4-nofpu ;;
+- sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4 ;;
++ sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4,mj2 ;;
+ sh*-*-netbsd*) sh_multilibs=m3,m3e,m4 ;;
+- *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single ;;
++ *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single,mj2 ;;
+ esac
+ if test x$with_fp = xno; then
+ sh_multilibs="`echo $sh_multilibs|sed -e s/m4/sh4-nofpu/ -e s/,m4-[^,]*//g -e s/,m[23]e// -e s/m2a,m2a-single/m2a-nofpu/ -e s/m5-..m....,//g`"
+@@ -2758,7 +2759,8 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
+ m2a | m2a-single | m2a-single-only | m2a-nofpu | \
+ m5-64media | m5-64media-nofpu | \
+ m5-32media | m5-32media-nofpu | \
+- m5-compact | m5-compact-nofpu)
++ m5-compact | m5-compact-nofpu | \
++ mj2)
+ # TM_MULTILIB_CONFIG is used by t-sh for the non-endian multilib definition
+ # It is passed to MULTIILIB_OPTIONS verbatim.
+ TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG}/${sh_multilib}"
+@@ -2775,7 +2777,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
+ done
+ TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's:^/::'`
+ if test x${enable_incomplete_targets} = xyes ; then
+- tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SH5_32MEDIA=1 SUPPORT_SH5_32MEDIA_NOFPU=1 SUPPORT_SH5_64MEDIA=1 SUPPORT_SH5_64MEDIA_NOFPU=1"
++ tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SH5_32MEDIA=1 SUPPORT_SH5_32MEDIA_NOFPU=1 SUPPORT_SH5_64MEDIA=1 SUPPORT_SH5_64MEDIA_NOFPU=1 SUPPORT_SHJ2=1"
+ fi
+ tm_file="$tm_file ./sysroot-suffix.h"
+ tmake_file="$tmake_file t-sysroot-suffix"
+@@ -4106,6 +4109,8 @@
+ ;;
+ m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al)
+ ;;
++ mj2)
++ ;;
+ *)
+ echo "Unknown CPU used in --with-cpu=$with_cpu, known values:" 1>&2
+ echo "m1 m2 m2e m3 m3e m4 m4-single m4-single-only m4-nofpu" 1>&2
+@@ -4456,7 +4458,7 @@ case ${target} in
+ tmake_file="rs6000/t-rs6000 ${tmake_file}"
+ ;;
+
+- sh[123456ble]*-*-* | sh-*-*)
++ sh[123456blej]*-*-* | sh-*-*)
+ c_target_objs="${c_target_objs} sh-c.o"
+ cxx_target_objs="${cxx_target_objs} sh-c.o"
+ ;;
+diff --git a/gcc/config/sh/sh-protos.h b/gcc/config/sh/sh-protos.h
+index b08120d..63b77fa 100644
+--- a/gcc/config/sh/sh-protos.h
++++ b/gcc/config/sh/sh-protos.h
+@@ -45,6 +45,7 @@ struct sh_atomic_model
+ hard_llcs,
+ soft_tcb,
+ soft_imask,
++ hard_cas,
+
+ num_models
+ };
+@@ -88,6 +89,9 @@ extern const sh_atomic_model& selected_atomic_model (void);
+ #define TARGET_ATOMIC_SOFT_IMASK \
+ (selected_atomic_model ().type == sh_atomic_model::soft_imask)
+
++#define TARGET_ATOMIC_HARD_CAS \
++ (selected_atomic_model ().type == sh_atomic_model::hard_cas)
++
+ #ifdef RTX_CODE
+ extern rtx sh_fsca_sf2int (void);
+ extern rtx sh_fsca_int2sf (void);
+diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
+index 0b18ce5..bdf96e2 100644
+--- a/gcc/config/sh/sh.c
++++ b/gcc/config/sh/sh.c
+@@ -692,6 +692,7 @@ parse_validate_atomic_model_option (const char* str)
+ model_names[sh_atomic_model::hard_llcs] = "hard-llcs";
+ model_names[sh_atomic_model::soft_tcb] = "soft-tcb";
+ model_names[sh_atomic_model::soft_imask] = "soft-imask";
++ model_names[sh_atomic_model::hard_cas] = "hard-cas";
+
+ const char* model_cdef_names[sh_atomic_model::num_models];
+ model_cdef_names[sh_atomic_model::none] = "NONE";
+@@ -699,6 +700,7 @@ parse_validate_atomic_model_option (const char* str)
+ model_cdef_names[sh_atomic_model::hard_llcs] = "HARD_LLCS";
+ model_cdef_names[sh_atomic_model::soft_tcb] = "SOFT_TCB";
+ model_cdef_names[sh_atomic_model::soft_imask] = "SOFT_IMASK";
++ model_cdef_names[sh_atomic_model::hard_cas] = "HARD_CAS";
+
+ sh_atomic_model ret;
+ ret.type = sh_atomic_model::none;
+@@ -780,6 +782,9 @@ got_mode_name:;
+ if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE)
+ err_ret ("cannot use atomic model %s in user mode", ret.name);
+
++ if (ret.type == sh_atomic_model::hard_cas && !TARGET_SHJ2)
++ err_ret ("atomic model %s is only available J2 targets", ret.name);
++
+ return ret;
+
+ #undef err_ret
+@@ -845,6 +850,8 @@ sh_option_override (void)
+ sh_cpu = PROCESSOR_SH2E;
+ if (TARGET_SH2A)
+ sh_cpu = PROCESSOR_SH2A;
++ if (TARGET_SHJ2)
++ sh_cpu = PROCESSOR_SHJ2;
+ if (TARGET_SH3)
+ sh_cpu = PROCESSOR_SH3;
+ if (TARGET_SH3E)
+diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
+index 7187c23..9d0d1d0 100644
+--- a/gcc/config/sh/sh.h
++++ b/gcc/config/sh/sh.h
+@@ -106,6 +106,7 @@ extern int code_for_indirect_jump_scratch;
+ #define SUPPORT_SH4_SINGLE 1
+ #define SUPPORT_SH2A 1
+ #define SUPPORT_SH2A_SINGLE 1
++#define SUPPORT_SHJ2 1
+ #endif
+
+ #define TARGET_DIVIDE_INV \
+@@ -157,6 +158,7 @@ extern int code_for_indirect_jump_scratch;
+ #define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
+ #define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
+ #define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
++#define SELECT_SHJ2 (MASK_SHJ2 | SELECT_SH2)
+
+ #if SUPPORT_SH1
+ #define SUPPORT_SH2 1
+@@ -164,6 +166,7 @@ extern int code_for_indirect_jump_scratch;
+ #if SUPPORT_SH2
+ #define SUPPORT_SH3 1
+ #define SUPPORT_SH2A_NOFPU 1
++#define SUPPORT_SHJ2 1
+ #endif
+ #if SUPPORT_SH3
+ #define SUPPORT_SH4_NOFPU 1
+@@ -211,7 +214,7 @@ extern int code_for_indirect_jump_scratch;
+ #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
+ | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
+ | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5 \
+- | MASK_FPU_SINGLE_ONLY)
++ | MASK_FPU_SINGLE_ONLY | MASK_SHJ2)
+
+ /* This defaults us to big-endian. */
+ #ifndef TARGET_ENDIAN_DEFAULT
+@@ -289,8 +292,8 @@ extern int code_for_indirect_jump_scratch;
+ %{m5-compact*:--isa=SHcompact} \
+ %{m5-32media*:--isa=SHmedia --abi=32} \
+ %{m5-64media*:--isa=SHmedia --abi=64} \
+-%{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}"
+-
++%{m4al:-dsp} %{mcut2-workaround:-cut2-workaround} \
++%{mj2:-isa=j2}"
+ #define ASM_SPEC SH_ASM_SPEC
+
+ #ifndef SUBTARGET_ASM_ENDIAN_SPEC
+@@ -1853,7 +1856,7 @@ struct sh_args {
+
+ /* Nonzero if the target supports dynamic shift instructions
+ like shad and shld. */
+-#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A)
++#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A || TARGET_SHJ2)
+
+ /* The cost of using the dynamic shift insns (shad, shld) are the same
+ if they are available. If they are not available a library function will
+@@ -2185,6 +2188,7 @@ enum processor_type {
+ PROCESSOR_SH2,
+ PROCESSOR_SH2E,
+ PROCESSOR_SH2A,
++ PROCESSOR_SHJ2,
+ PROCESSOR_SH3,
+ PROCESSOR_SH3E,
+ PROCESSOR_SH4,
+diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt
+index 1026c73..bac47ed 100644
+--- a/gcc/config/sh/sh.opt
++++ b/gcc/config/sh/sh.opt
+@@ -71,6 +71,10 @@ m2e
+ Target RejectNegative Condition(SUPPORT_SH2E)
+ Generate SH2e code.
+
++mj2
++Target RejectNegative Mask(SHJ2) Condition(SUPPORT_SHJ2)
++Generate J2 code.
++
+ m3
+ Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3)
+ Generate SH3 code.
+diff --git a/gcc/config/sh/sync.md b/gcc/config/sh/sync.md
+index 6f1337b..cff57b8 100644
+--- a/gcc/config/sh/sync.md
++++ b/gcc/config/sh/sync.md
+@@ -240,6 +240,9 @@
+ || (TARGET_SH4A && <MODE>mode == SImode && !TARGET_ATOMIC_STRICT))
+ atomic_insn = gen_atomic_compare_and_swap<mode>_hard (old_val, mem,
+ exp_val, new_val);
++ else if (TARGET_ATOMIC_HARD_CAS && <MODE>mode == SImode)
++ atomic_insn = gen_atomic_compare_and_swap<mode>_cas (old_val, mem,
++ exp_val, new_val);
+ else if (TARGET_ATOMIC_SOFT_GUSA)
+ atomic_insn = gen_atomic_compare_and_swap<mode>_soft_gusa (old_val, mem,
+ exp_val, new_val);
+@@ -306,6 +309,57 @@
+ }
+ [(set_attr "length" "14")])
+
++(define_expand "atomic_compare_and_swapsi_cas"
++ [(set (match_operand:SI 0 "register_operand" "=r")
++ (unspec_volatile:SI
++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
++ (match_operand:SI 2 "register_operand" "r")
++ (match_operand:SI 3 "register_operand" "r")]
++ UNSPECV_CMPXCHG_1))]
++ "TARGET_ATOMIC_HARD_CAS"
++{
++ rtx mem = gen_rtx_REG (SImode, 0);
++ emit_move_insn (mem, force_reg (SImode, XEXP (operands[1], 0)));
++ emit_insn (gen_shj2_cas (operands[0], mem, operands[2], operands[3]));
++ DONE;
++})
++
++(define_insn "shj2_cas"
++ [(set (match_operand:SI 0 "register_operand" "=&r")
++ (unspec_volatile:SI
++ [(match_operand:SI 1 "register_operand" "=r")
++ (match_operand:SI 2 "register_operand" "r")
++ (match_operand:SI 3 "register_operand" "0")]
++ UNSPECV_CMPXCHG_1))
++ (set (reg:SI T_REG)
++ (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3))]
++ "TARGET_ATOMIC_HARD_CAS"
++ "cas.l %2,%0,@%1"
++ [(set_attr "length" "2")]
++)
++
++(define_expand "atomic_compare_and_swapqi_cas"
++ [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
++ (unspec_volatile:SI
++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
++ (match_operand:SI 2 "arith_operand" "rI08")
++ (match_operand:SI 3 "arith_operand" "rI08")]
++ UNSPECV_CMPXCHG_1))]
++ "TARGET_ATOMIC_HARD_CAS"
++{FAIL;}
++)
++
++(define_expand "atomic_compare_and_swaphi_cas"
++ [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
++ (unspec_volatile:SI
++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
++ (match_operand:SI 2 "arith_operand" "rI08")
++ (match_operand:SI 3 "arith_operand" "rI08")]
++ UNSPECV_CMPXCHG_1))]
++ "TARGET_ATOMIC_HARD_CAS"
++{FAIL;}
++)
++
+ ;; The QIHImode llcs patterns modify the address register of the memory
+ ;; operand. In order to express that, we have to open code the memory
+ ;; operand. Initially the insn is expanded like every other atomic insn
+diff --git a/gcc/config/sh/t-sh b/gcc/config/sh/t-sh
+index 348cc0b..8e6bdaf 100644
+--- a/gcc/config/sh/t-sh
++++ b/gcc/config/sh/t-sh
+@@ -52,7 +52,7 @@ MULTILIB_MATCHES = $(shell \
+ m4-single,m4-100-single,m4-200-single,m4-300-single,m4a-single \
+ m4,m4-100,m4-200,m4-300,m4a \
+ m5-32media,m5-compact,m5-32media \
+- m5-32media-nofpu,m5-compact-nofpu,m5-32media-nofpu; do \
++ m5-32media-nofpu,m5-compact-nofpu,m5-32media-nofpu,mj2; do \
+ subst= ; \
+ for lib in `echo $$abi|tr , ' '` ; do \
+ if test "`echo $$multilibs|sed s/$$lib//`" != "$$multilibs"; then \
+@@ -65,9 +65,9 @@ MULTILIB_MATCHES = $(shell \
+
+ # SH1 and SH2A support big endian only.
+ ifeq ($(DEFAULT_ENDIAN),ml)
+-MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG)
++MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG)
+ else
+-MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG)
++MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG)
+ endif
+
+ MULTILIB_OSDIRNAMES = \
+@@ -96,6 +96,7 @@ MULTILIB_OSDIRNAMES = \
+ m5-compact-nofpu=!m5-compact-nofpu $(OTHER_ENDIAN)/m5-compact-nofpu=!$(OTHER_ENDIAN)/m5-compact-nofpu \
+ m5-64media=!m5-64media $(OTHER_ENDIAN)/m5-64media=!$(OTHER_ENDIAN)/m5-64media \
+ m5-64media-nofpu=!m5-64media-nofpu $(OTHER_ENDIAN)/m5-64media-nofpu=!$(OTHER_ENDIAN)/m5-64media-nofpu
++ mj2=!j2
+
+ $(out_object_file): gt-sh.h
+ gt-sh.h : s-gtype ; @true
--- /dev/null
+--- gcc-5.2.0.orig/gcc/config/gnu-user.h 2015-01-05 12:33:28.000000000 +0000
++++ gcc-5.2.0/gcc/config/gnu-user.h 2015-08-25 08:15:18.354957759 +0000
+@@ -42,8 +42,8 @@
+
+ #if defined HAVE_LD_PIE
+ #define GNU_USER_TARGET_STARTFILE_SPEC \
+- "%{!shared: %{pg|p|profile:gcrt1.o%s;pie:Scrt1.o%s;:crt1.o%s}} \
+- crti.o%s %{static:crtbeginT.o%s;shared|pie:crtbeginS.o%s;:crtbegin.o%s} \
++ "%{!shared: %{pg|p|profile:gcrt1.o%s;pie:%{static:rcrt1.o%s;:Scrt1.o%s};:crt1.o%s}} \
++ crti.o%s %{shared|pie:crtbeginS.o%s;static:crtbeginT.o%s;:crtbegin.o%s} \
+ %{fvtable-verify=none:%s; \
+ fvtable-verify=preinit:vtv_start_preinit.o%s; \
+ fvtable-verify=std:vtv_start.o%s}"
+--- gcc-5.2.0.orig/gcc/gcc.c 2015-03-10 09:37:41.000000000 +0000
++++ gcc-5.2.0/gcc/gcc.c 2015-09-30 00:25:33.225927941 +0000
+@@ -739,7 +739,7 @@
+
+ #ifndef LINK_PIE_SPEC
+ #ifdef HAVE_LD_PIE
+-#define LINK_PIE_SPEC "%{pie:-pie} "
++#define LINK_PIE_SPEC "%{pie:-pie %{static:--no-dynamic-linker}} "
+ #else
+ #define LINK_PIE_SPEC "%{pie:} "
+ #endif
--- /dev/null
+diff --git a/gcc/config.gcc b/gcc/config.gcc
+index 3779369..a6d95ca 100644
+--- a/gcc/config.gcc
++++ b/gcc/config.gcc
+@@ -3101,6 +3101,12 @@ case ${target} in
+ ;;
+ esac
+
++case "x${enable_default_pie}" in
++xyes)
++ tm_defines="${tm_defines} ENABLE_DEFAULT_PIE=1"
++ ;;
++esac
++
+ t=
+ all_defaults="abi cpu arch tune schedule float mode fpu divide"
+ for option in $all_defaults
+--- gcc-5.2.0.orig/gcc/gcc.c 2015-03-10 09:37:41.000000000 +0000
++++ gcc-5.2.0/gcc/gcc.c 2015-08-25 07:47:12.895060530 +0000
+@@ -1012,10 +1012,19 @@
+ #define CILK_SELF_SPECS "%{fcilkplus: -pthread}"
+ #endif
+
++/* Default to PIE */
++#ifndef PIE_SELF_SPECS
++#ifdef ENABLE_DEFAULT_PIE
++#define PIE_SELF_SPECS "%{shared|pie|r|nostdlib|nopie|no-pie:;:-pie} %{fpic|fPIC|fpie|fPIE|fno-pic|fno-PIC|fno-pie|fno-PIE|D__KERNEL__:;:-fPIE}"
++#else
++#define PIE_SELF_SPECS ""
++#endif
++#endif
++
+ static const char *const driver_self_specs[] = {
+ "%{fdump-final-insns:-fdump-final-insns=.} %<fdump-final-insns",
+ DRIVER_SELF_SPECS, CONFIGURE_SPECS, GOMP_SELF_SPECS, GTM_SELF_SPECS,
+- CILK_SELF_SPECS
++ CILK_SELF_SPECS, PIE_SELF_SPECS
+ };
+
+ #ifndef OPTION_DEFAULT_SPECS
--- /dev/null
+diff --git a/gcc/config.gcc b/gcc/config.gcc
+index bf26776..ed118f3 100644
+--- a/gcc/config.gcc
++++ b/gcc/config.gcc
+@@ -2621,6 +2621,9 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
+ tm_file="${tm_file} dbxelf.h elfos.h sh/elf.h"
+ case ${target} in
+ sh*-*-linux*) tmake_file="${tmake_file} sh/t-linux"
++ if test x$enable_fdpic = xyes; then
++ tm_defines="$tm_defines FDPIC_DEFAULT=1"
++ fi
+ tm_file="${tm_file} gnu-user.h linux.h glibc-stdint.h sh/linux.h" ;;
+ sh*-*-netbsd*)
+ tm_file="${tm_file} netbsd.h netbsd-elf.h sh/netbsd-elf.h"
+diff --git a/gcc/config/sh/constraints.md b/gcc/config/sh/constraints.md
+index 4d1eb2d..41c88a2 100644
+--- a/gcc/config/sh/constraints.md
++++ b/gcc/config/sh/constraints.md
+@@ -25,6 +25,7 @@
+ ;; Bsc: SCRATCH - for the scratch register in movsi_ie in the
+ ;; fldi0 / fldi0 cases
+ ;; Cxx: Constants other than only CONST_INT
++;; Ccl: call site label
+ ;; Css: signed 16-bit constant, literal or symbolic
+ ;; Csu: unsigned 16-bit constant, literal or symbolic
+ ;; Csy: label or symbol
+@@ -233,6 +234,11 @@ (define_constraint "Bsc"
+ hence mova is being used, hence do not select this pattern."
+ (match_code "scratch"))
+
++(define_constraint "Ccl"
++ "A call site label, for bsrf."
++ (and (match_code "unspec")
++ (match_test "XINT (op, 1) == UNSPEC_CALLER")))
++
+ (define_constraint "Css"
+ "A signed 16-bit constant, literal or symbolic."
+ (and (match_code "const")
+diff --git a/gcc/config/sh/linux.h b/gcc/config/sh/linux.h
+index a9dd43a..5d4dd1f 100644
+--- a/gcc/config/sh/linux.h
++++ b/gcc/config/sh/linux.h
+@@ -69,7 +69,8 @@ along with GCC; see the file COPYING3. If not see
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
+
+ #undef SUBTARGET_LINK_EMUL_SUFFIX
+-#define SUBTARGET_LINK_EMUL_SUFFIX "_linux"
++#define SUBTARGET_LINK_EMUL_SUFFIX "%{mfdpic:_fd;:_linux}"
++
+ #undef SUBTARGET_LINK_SPEC
+ #define SUBTARGET_LINK_SPEC \
+ "%{shared:-shared} \
+diff --git a/gcc/config/sh/sh-c.c b/gcc/config/sh/sh-c.c
+index a98c148..01a12e6 100644
+--- a/gcc/config/sh/sh-c.c
++++ b/gcc/config/sh/sh-c.c
+@@ -141,6 +141,11 @@ sh_cpu_cpp_builtins (cpp_reader* pfile)
+ builtin_define ("__HITACHI__");
+ if (TARGET_FMOVD)
+ builtin_define ("__FMOVD_ENABLED__");
++ if (TARGET_FDPIC)
++ {
++ builtin_define ("__SH_FDPIC__");
++ builtin_define ("__FDPIC__");
++ }
+ builtin_define (TARGET_LITTLE_ENDIAN
+ ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__");
+
+diff --git a/gcc/config/sh/sh-mem.cc b/gcc/config/sh/sh-mem.cc
+index 23a7287..4d92f54 100644
+--- a/gcc/config/sh/sh-mem.cc
++++ b/gcc/config/sh/sh-mem.cc
+@@ -123,29 +123,30 @@ expand_block_move (rtx *operands)
+ rtx r4 = gen_rtx_REG (SImode, 4);
+ rtx r5 = gen_rtx_REG (SImode, 5);
+
+- function_symbol (func_addr_rtx, "__movmemSI12_i4", SFUNC_STATIC);
++ rtx lab = function_symbol (func_addr_rtx, "__movmemSI12_i4",
++ SFUNC_STATIC).lab;
+ force_into (XEXP (operands[0], 0), r4);
+ force_into (XEXP (operands[1], 0), r5);
+- emit_insn (gen_block_move_real_i4 (func_addr_rtx));
++ emit_insn (gen_block_move_real_i4 (func_addr_rtx, lab));
+ return true;
+ }
+ else if (! optimize_size)
+ {
+- const char *entry_name;
+ rtx func_addr_rtx = gen_reg_rtx (Pmode);
+- int dwords;
+ rtx r4 = gen_rtx_REG (SImode, 4);
+ rtx r5 = gen_rtx_REG (SImode, 5);
+ rtx r6 = gen_rtx_REG (SImode, 6);
+
+- entry_name = (bytes & 4 ? "__movmem_i4_odd" : "__movmem_i4_even");
+- function_symbol (func_addr_rtx, entry_name, SFUNC_STATIC);
++ rtx lab = function_symbol (func_addr_rtx, bytes & 4
++ ? "__movmem_i4_odd"
++ : "__movmem_i4_even",
++ SFUNC_STATIC).lab;
+ force_into (XEXP (operands[0], 0), r4);
+ force_into (XEXP (operands[1], 0), r5);
+
+- dwords = bytes >> 3;
++ int dwords = bytes >> 3;
+ emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1)));
+- emit_insn (gen_block_lump_real_i4 (func_addr_rtx));
++ emit_insn (gen_block_lump_real_i4 (func_addr_rtx, lab));
+ return true;
+ }
+ else
+@@ -159,10 +160,10 @@ expand_block_move (rtx *operands)
+ rtx r5 = gen_rtx_REG (SImode, 5);
+
+ sprintf (entry, "__movmemSI%d", bytes);
+- function_symbol (func_addr_rtx, entry, SFUNC_STATIC);
++ rtx lab = function_symbol (func_addr_rtx, entry, SFUNC_STATIC).lab;
+ force_into (XEXP (operands[0], 0), r4);
+ force_into (XEXP (operands[1], 0), r5);
+- emit_insn (gen_block_move_real (func_addr_rtx));
++ emit_insn (gen_block_move_real (func_addr_rtx, lab));
+ return true;
+ }
+
+@@ -176,7 +177,7 @@ expand_block_move (rtx *operands)
+ rtx r5 = gen_rtx_REG (SImode, 5);
+ rtx r6 = gen_rtx_REG (SImode, 6);
+
+- function_symbol (func_addr_rtx, "__movmem", SFUNC_STATIC);
++ rtx lab = function_symbol (func_addr_rtx, "__movmem", SFUNC_STATIC).lab;
+ force_into (XEXP (operands[0], 0), r4);
+ force_into (XEXP (operands[1], 0), r5);
+
+@@ -189,7 +190,7 @@ expand_block_move (rtx *operands)
+ final_switch = 16 - ((bytes / 4) % 16);
+ while_loop = ((bytes / 4) / 16 - 1) * 16;
+ emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
+- emit_insn (gen_block_lump_real (func_addr_rtx));
++ emit_insn (gen_block_lump_real (func_addr_rtx, lab));
+ return true;
+ }
+
+diff --git a/gcc/config/sh/sh-protos.h b/gcc/config/sh/sh-protos.h
+index f94459f..c64a948 100644
+--- a/gcc/config/sh/sh-protos.h
++++ b/gcc/config/sh/sh-protos.h
+@@ -377,7 +377,19 @@ extern void fpscr_set_from_mem (int, HARD_REG_SET);
+ extern void sh_pr_interrupt (struct cpp_reader *);
+ extern void sh_pr_trapa (struct cpp_reader *);
+ extern void sh_pr_nosave_low_regs (struct cpp_reader *);
+-extern rtx function_symbol (rtx, const char *, enum sh_function_kind);
++
++struct function_symbol_result
++{
++ function_symbol_result (void) : sym (NULL), lab (NULL) { }
++ function_symbol_result (rtx s, rtx l) : sym (s), lab (l) { }
++
++ rtx sym;
++ rtx lab;
++};
++
++extern function_symbol_result function_symbol (rtx, const char *,
++ sh_function_kind);
++extern rtx sh_get_fdpic_reg_initial_val (void);
+ extern rtx sh_get_pr_initial_val (void);
+
+ extern void sh_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree,
+@@ -396,4 +408,5 @@ extern bool sh_hard_regno_mode_ok (unsigned int, machine_mode);
+ extern machine_mode sh_hard_regno_caller_save_mode (unsigned int, unsigned int,
+ machine_mode);
+ extern bool sh_can_use_simple_return_p (void);
++extern rtx sh_load_function_descriptor (rtx);
+ #endif /* ! GCC_SH_PROTOS_H */
+diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
+index 904201b..e6a0b1e 100644
+--- a/gcc/config/sh/sh.c
++++ b/gcc/config/sh/sh.c
+@@ -268,6 +268,7 @@ static rtx sh_expand_builtin (tree, rtx, rtx, machine_mode, int);
+ static void sh_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
+ HOST_WIDE_INT, tree);
+ static void sh_file_start (void);
++static bool sh_assemble_integer (rtx, unsigned int, int);
+ static bool flow_dependent_p (rtx, rtx);
+ static void flow_dependent_p_1 (rtx, const_rtx, void *);
+ static int shiftcosts (rtx);
+@@ -276,6 +277,7 @@ static int addsubcosts (rtx);
+ static int multcosts (rtx);
+ static bool unspec_caller_rtx_p (rtx);
+ static bool sh_cannot_copy_insn_p (rtx_insn *);
++static bool sh_cannot_force_const_mem_p (machine_mode, rtx);
+ static bool sh_rtx_costs (rtx, int, int, int, int *, bool);
+ static int sh_address_cost (rtx, machine_mode, addr_space_t, bool);
+ static int sh_pr_n_sets (void);
+@@ -421,6 +423,9 @@ static const struct attribute_spec sh_attribute_table[] =
+ #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
+ #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
+
++#undef TARGET_ASM_INTEGER
++#define TARGET_ASM_INTEGER sh_assemble_integer
++
+ #undef TARGET_REGISTER_MOVE_COST
+ #define TARGET_REGISTER_MOVE_COST sh_register_move_cost
+
+@@ -679,6 +684,9 @@ static const struct attribute_spec sh_attribute_table[] =
+ #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
+ #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 0x80
+
++#undef TARGET_CANNOT_FORCE_CONST_MEM
++#define TARGET_CANNOT_FORCE_CONST_MEM sh_cannot_force_const_mem_p
++
+ struct gcc_target targetm = TARGET_INITIALIZER;
+ \f
+
+@@ -996,6 +1004,13 @@ sh_option_override (void)
+ if (! global_options_set.x_TARGET_ZDCBRANCH && TARGET_HARD_SH4)
+ TARGET_ZDCBRANCH = 1;
+
++ /* FDPIC code is a special form of PIC, and the vast majority of code
++ generation constraints that apply to PIC also apply to FDPIC, so we
++ set flag_pic to avoid the need to check TARGET_FDPIC everywhere
++ flag_pic is checked. */
++ if (TARGET_FDPIC && !flag_pic)
++ flag_pic = 2;
++
+ for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
+ if (! VALID_REGISTER_P (regno))
+ sh_register_names[regno][0] = '\0';
+@@ -1687,6 +1702,14 @@ sh_asm_output_addr_const_extra (FILE *file, rtx x)
+ output_addr_const (file, XVECEXP (x, 0, 1));
+ fputs ("-.)", file);
+ break;
++ case UNSPEC_GOTFUNCDESC:
++ output_addr_const (file, XVECEXP (x, 0, 0));
++ fputs ("@GOTFUNCDESC", file);
++ break;
++ case UNSPEC_GOTOFFFUNCDESC:
++ output_addr_const (file, XVECEXP (x, 0, 0));
++ fputs ("@GOTOFFFUNCDESC", file);
++ break;
+ default:
+ return false;
+ }
+@@ -1871,6 +1894,9 @@ prepare_move_operands (rtx operands[], machine_mode mode)
+ {
+ case TLS_MODEL_GLOBAL_DYNAMIC:
+ tga_ret = gen_rtx_REG (Pmode, R0_REG);
++ if (TARGET_FDPIC)
++ emit_move_insn (gen_rtx_REG (Pmode, PIC_REG),
++ sh_get_fdpic_reg_initial_val ());
+ emit_call_insn (gen_tls_global_dynamic (tga_ret, op1));
+ tmp = gen_reg_rtx (Pmode);
+ emit_move_insn (tmp, tga_ret);
+@@ -1879,6 +1905,9 @@ prepare_move_operands (rtx operands[], machine_mode mode)
+
+ case TLS_MODEL_LOCAL_DYNAMIC:
+ tga_ret = gen_rtx_REG (Pmode, R0_REG);
++ if (TARGET_FDPIC)
++ emit_move_insn (gen_rtx_REG (Pmode, PIC_REG),
++ sh_get_fdpic_reg_initial_val ());
+ emit_call_insn (gen_tls_local_dynamic (tga_ret, op1));
+
+ tmp = gen_reg_rtx (Pmode);
+@@ -1896,6 +1925,9 @@ prepare_move_operands (rtx operands[], machine_mode mode)
+ case TLS_MODEL_INITIAL_EXEC:
+ tga_op1 = !can_create_pseudo_p () ? op0 : gen_reg_rtx (Pmode);
+ tmp = gen_sym2GOTTPOFF (op1);
++ if (TARGET_FDPIC)
++ emit_move_insn (gen_rtx_REG (Pmode, PIC_REG),
++ sh_get_fdpic_reg_initial_val ());
+ emit_insn (gen_tls_initial_exec (tga_op1, tmp));
+ op1 = tga_op1;
+ break;
+@@ -1922,6 +1954,22 @@ prepare_move_operands (rtx operands[], machine_mode mode)
+ operands[1] = op1;
+ }
+ }
++
++ if (SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P)
++ {
++ rtx base, offset;
++ split_const (operands[1], &base, &offset);
++
++ if (GET_CODE (base) == SYMBOL_REF
++ && !offset_within_block_p (base, INTVAL (offset)))
++ {
++ rtx tmp = can_create_pseudo_p () ? gen_reg_rtx (mode) : operands[0];
++ emit_move_insn (tmp, base);
++ if (!arith_operand (offset, mode))
++ offset = force_reg (mode, offset);
++ emit_insn (gen_add3_insn (operands[0], tmp, offset));
++ }
++ }
+ }
+
+ /* Implement the canonicalize_comparison target hook for the combine
+@@ -3026,6 +3074,24 @@ sh_file_start (void)
+ }
+ }
+ \f
++/* Implementation of TARGET_ASM_INTEGER for SH. Pointers to functions
++ need to be output as pointers to function descriptors for
++ FDPIC. */
++
++static bool
++sh_assemble_integer (rtx value, unsigned int size, int aligned_p)
++{
++ if (TARGET_FDPIC && size == UNITS_PER_WORD
++ && GET_CODE (value) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (value))
++ {
++ fputs ("\t.long\t", asm_out_file);
++ output_addr_const (asm_out_file, value);
++ fputs ("@FUNCDESC\n", asm_out_file);
++ return true;
++ }
++ return default_assemble_integer (value, size, aligned_p);
++}
++\f
+ /* Check if PAT includes UNSPEC_CALLER unspec pattern. */
+ static bool
+ unspec_caller_rtx_p (rtx pat)
+@@ -3061,6 +3127,17 @@ sh_cannot_copy_insn_p (rtx_insn *insn)
+ return false;
+
+ pat = PATTERN (insn);
++
++ if (GET_CODE (pat) == CLOBBER || GET_CODE (pat) == USE)
++ return false;
++
++ if (TARGET_FDPIC && GET_CODE (pat) == PARALLEL)
++ {
++ rtx t = XVECEXP (pat, 0, XVECLEN (pat, 0) - 1);
++ if (GET_CODE (t) == USE && unspec_caller_rtx_p (XEXP (t, 0)))
++ return true;
++ }
++
+ if (GET_CODE (pat) != SET)
+ return false;
+ pat = SET_SRC (pat);
+@@ -4102,8 +4179,8 @@ expand_ashiftrt (rtx *operands)
+ /* Load the value into an arg reg and call a helper. */
+ emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
+ sprintf (func, "__ashiftrt_r4_%d", value);
+- function_symbol (wrk, func, SFUNC_STATIC);
+- emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
++ rtx lab = function_symbol (wrk, func, SFUNC_STATIC).lab;
++ emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk, lab));
+ emit_move_insn (operands[0], gen_rtx_REG (SImode, 4));
+ return true;
+ }
+@@ -7954,7 +8031,8 @@ sh_expand_prologue (void)
+ stack_usage += d;
+ }
+
+- if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
++ if (flag_pic && !TARGET_FDPIC
++ && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
+ emit_insn (gen_GOTaddr2picreg (const0_rtx));
+
+ if (SHMEDIA_REGS_STACK_ADJUST ())
+@@ -10458,7 +10536,9 @@ nonpic_symbol_mentioned_p (rtx x)
+ || XINT (x, 1) == UNSPEC_PLT
+ || XINT (x, 1) == UNSPEC_PCREL
+ || XINT (x, 1) == UNSPEC_SYMOFF
+- || XINT (x, 1) == UNSPEC_PCREL_SYMOFF))
++ || XINT (x, 1) == UNSPEC_PCREL_SYMOFF
++ || XINT (x, 1) == UNSPEC_GOTFUNCDESC
++ || XINT (x, 1) == UNSPEC_GOTOFFFUNCDESC))
+ return false;
+
+ fmt = GET_RTX_FORMAT (GET_CODE (x));
+@@ -10493,7 +10573,26 @@ legitimize_pic_address (rtx orig, machine_mode mode ATTRIBUTE_UNUSED,
+ if (reg == NULL_RTX)
+ reg = gen_reg_rtx (Pmode);
+
+- emit_insn (gen_symGOTOFF2reg (reg, orig));
++ if (TARGET_FDPIC
++ && GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (orig))
++ {
++ /* Weak functions may be NULL which doesn't work with
++ GOTOFFFUNCDESC because the runtime offset is not known. */
++ if (SYMBOL_REF_WEAK (orig))
++ emit_insn (gen_symGOTFUNCDESC2reg (reg, orig));
++ else
++ emit_insn (gen_symGOTOFFFUNCDESC2reg (reg, orig));
++ }
++ else if (TARGET_FDPIC
++ && (GET_CODE (orig) == LABEL_REF
++ || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_DECL (orig)
++ && (TREE_READONLY (SYMBOL_REF_DECL (orig))
++ || SYMBOL_REF_EXTERNAL_P (orig)
++ || DECL_SECTION_NAME(SYMBOL_REF_DECL (orig))))))
++ /* In FDPIC, GOTOFF can only be used for writable data. */
++ emit_insn (gen_symGOT2reg (reg, orig));
++ else
++ emit_insn (gen_symGOTOFF2reg (reg, orig));
+ return reg;
+ }
+ else if (GET_CODE (orig) == SYMBOL_REF)
+@@ -10501,7 +10600,10 @@ legitimize_pic_address (rtx orig, machine_mode mode ATTRIBUTE_UNUSED,
+ if (reg == NULL_RTX)
+ reg = gen_reg_rtx (Pmode);
+
+- emit_insn (gen_symGOT2reg (reg, orig));
++ if (TARGET_FDPIC && SYMBOL_REF_FUNCTION_P (orig))
++ emit_insn (gen_symGOTFUNCDESC2reg (reg, orig));
++ else
++ emit_insn (gen_symGOT2reg (reg, orig));
+ return reg;
+ }
+ return orig;
+@@ -11539,8 +11641,39 @@ sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED)
+ 5 0008 00000000 l1: .long area
+ 6 000c 00000000 l2: .long function
+
++ FDPIC needs a form that includes a function descriptor and
++ code to load the GOT register:
++ 0 0000 00000000 .long l0
++ 1 0004 00000000 .long gotval
++ 2 0008 D302 l0: mov.l l1,r3
++ 3 000a D203 mov.l l2,r2
++ 4 000c 6122 mov.l @r2,r1
++ 5 000e 5C21 mov.l @(4,r2),r12
++ 6 0010 412B jmp @r1
++ 7 0012 0009 nop
++ 8 0014 00000000 l1: .long area
++ 9 0018 00000000 l2: .long function
++
+ SH5 (compact) uses r1 instead of r3 for the static chain. */
+
++/* Emit insns to store a value at memory address + offset. */
++static void
++sh_emit_storesi (rtx addr, HOST_WIDE_INT offset, rtx value)
++{
++ gcc_assert ((offset & 3) == 0);
++ emit_move_insn (offset == 0
++ ? change_address (addr, SImode, NULL_RTX)
++ : adjust_address (addr, SImode, offset), value);
++}
++
++/* Emit insns to store w0 at addr + offset and w1 at addr + offset + 2. */
++static void
++sh_emit_storehi (rtx addr, HOST_WIDE_INT offset, uint16_t w0, uint16_t w1)
++{
++ sh_emit_storesi (addr, offset, gen_int_mode (TARGET_LITTLE_ENDIAN
++ ? (w0 | (w1 << 16))
++ : (w1 | (w0 << 16)), SImode));
++}
+
+ /* Emit RTL insns to initialize the variable parts of a trampoline.
+ FNADDR is an RTX for the address of the function's pure code.
+@@ -11675,20 +11808,34 @@ sh_trampoline_init (rtx tramp_mem, tree fndecl, rtx cxt)
+ emit_insn (gen_initialize_trampoline (tramp, cxt, fnaddr));
+ return;
+ }
+- emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX),
+- gen_int_mode (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301,
+- SImode));
+- emit_move_insn (adjust_address (tramp_mem, SImode, 4),
+- gen_int_mode (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009,
+- SImode));
+- emit_move_insn (adjust_address (tramp_mem, SImode, 8), cxt);
+- emit_move_insn (adjust_address (tramp_mem, SImode, 12), fnaddr);
++ if (TARGET_FDPIC)
++ {
++ rtx a = force_reg (Pmode, plus_constant (Pmode, XEXP (tramp_mem, 0), 8));
++
++ sh_emit_storesi (tramp_mem, 0, a);
++ sh_emit_storesi (tramp_mem, 4, sh_get_fdpic_reg_initial_val ());
++
++ sh_emit_storehi (tramp_mem, 8, 0xd302, 0xd203);
++ sh_emit_storehi (tramp_mem, 12, 0x6122, 0x5c21);
++ sh_emit_storehi (tramp_mem, 16, 0x412b, 0x0009);
++
++ sh_emit_storesi (tramp_mem, 20, cxt);
++ sh_emit_storesi (tramp_mem, 24, fnaddr);
++ }
++ else
++ {
++ sh_emit_storehi (tramp_mem, 0, 0xd202, 0xd301);
++ sh_emit_storehi (tramp_mem, 4, 0x422b, 0x0009);
++
++ sh_emit_storesi (tramp_mem, 8, cxt);
++ sh_emit_storesi (tramp_mem, 12, fnaddr);
++ }
+ if (TARGET_HARD_SH4 || TARGET_SH5)
+ {
+ if (!TARGET_INLINE_IC_INVALIDATE
+ || (!(TARGET_SH4A || TARGET_SH4_300) && TARGET_USERMODE))
+ emit_library_call (function_symbol (NULL, "__ic_invalidate",
+- FUNCTION_ORDINARY),
++ FUNCTION_ORDINARY).sym,
+ LCT_NORMAL, VOIDmode, 1, tramp, SImode);
+ else
+ emit_insn (gen_ic_invalidate_line (tramp));
+@@ -11718,7 +11865,7 @@ sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
+ && (! TARGET_SHCOMPACT
+ || crtl->args.info.stack_regs == 0)
+ && ! sh_cfun_interrupt_handler_p ()
+- && (! flag_pic
++ && (! flag_pic || TARGET_FDPIC
+ || (decl && ! (TREE_PUBLIC (decl) || DECL_WEAK (decl)))
+ || (decl && DECL_VISIBILITY (decl) != VISIBILITY_DEFAULT)));
+ }
+@@ -11732,7 +11879,7 @@ sh_expand_sym_label2reg (rtx reg, rtx sym, rtx lab, bool sibcall_p)
+
+ if (!is_weak && SYMBOL_REF_LOCAL_P (sym))
+ emit_insn (gen_sym_label2reg (reg, sym, lab));
+- else if (sibcall_p)
++ else if (sibcall_p && SYMBOL_REF_LOCAL_P (sym))
+ emit_insn (gen_symPCREL_label2reg (reg, sym, lab));
+ else
+ emit_insn (gen_symPLT_label2reg (reg, sym, lab));
+@@ -12733,8 +12880,16 @@ sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
+ #endif
+ if (TARGET_SH2 && flag_pic)
+ {
+- sibcall = gen_sibcall_pcrel (funexp, const0_rtx);
+- XEXP (XVECEXP (sibcall, 0, 2), 0) = scratch2;
++ if (TARGET_FDPIC)
++ {
++ sibcall = gen_sibcall_pcrel_fdpic (funexp, const0_rtx);
++ XEXP (XVECEXP (sibcall, 0, 3), 0) = scratch2;
++ }
++ else
++ {
++ sibcall = gen_sibcall_pcrel (funexp, const0_rtx);
++ XEXP (XVECEXP (sibcall, 0, 2), 0) = scratch2;
++ }
+ }
+ else
+ {
+@@ -12775,17 +12930,25 @@ sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
+ epilogue_completed = 0;
+ }
+
+-rtx
+-function_symbol (rtx target, const char *name, enum sh_function_kind kind)
+-{
+- rtx sym;
++/* Return an RTX pair for the address and call site label of a function
++ NAME of kind KIND, placing the result in TARGET if not NULL. For
++ SFUNC_STATIC, if FDPIC, the LAB member of result will be set to
++ (const_int 0) if jsr should be used, or a label_ref if bsrf should
++ be used. For FDPIC, both SFUNC_GOT and SFUNC_STATIC will return the
++ address of the function itself, not a function descriptor, so they
++ can only be used with functions not using the FDPIC register that
++ are known to be called directory without a PLT entry. */
+
++function_symbol_result
++function_symbol (rtx target, const char *name, sh_function_kind kind)
++{
+ /* If this is not an ordinary function, the name usually comes from a
+ string literal or an sprintf buffer. Make sure we use the same
+ string consistently, so that cse will be able to unify address loads. */
+ if (kind != FUNCTION_ORDINARY)
+ name = IDENTIFIER_POINTER (get_identifier (name));
+- sym = gen_rtx_SYMBOL_REF (Pmode, name);
++ rtx sym = gen_rtx_SYMBOL_REF (Pmode, name);
++ rtx lab = const0_rtx;
+ SYMBOL_REF_FLAGS (sym) = SYMBOL_FLAG_FUNCTION;
+ if (flag_pic)
+ switch (kind)
+@@ -12802,14 +12965,25 @@ function_symbol (rtx target, const char *name, enum sh_function_kind kind)
+ }
+ case SFUNC_STATIC:
+ {
+- /* ??? To allow cse to work, we use GOTOFF relocations.
+- We could add combiner patterns to transform this into
+- straight pc-relative calls with sym2PIC / bsrf when
+- label load and function call are still 1:1 and in the
+- same basic block during combine. */
+ rtx reg = target ? target : gen_reg_rtx (Pmode);
+
+- emit_insn (gen_symGOTOFF2reg (reg, sym));
++ if (TARGET_FDPIC)
++ {
++ /* We use PC-relative calls, since GOTOFF can only refer
++ to writable data. This works along with sh_sfunc_call. */
++ lab = PATTERN (gen_call_site ());
++ emit_insn (gen_sym_label2reg (reg, sym, lab));
++ }
++ else
++ {
++ /* ??? To allow cse to work, we use GOTOFF relocations.
++ we could add combiner patterns to transform this into
++ straight pc-relative calls with sym2PIC / bsrf when
++ label load and function call are still 1:1 and in the
++ same basic block during combine. */
++ emit_insn (gen_symGOTOFF2reg (reg, sym));
++ }
++
+ sym = reg;
+ break;
+ }
+@@ -12817,9 +12991,9 @@ function_symbol (rtx target, const char *name, enum sh_function_kind kind)
+ if (target && sym != target)
+ {
+ emit_move_insn (target, sym);
+- return target;
++ return function_symbol_result (target, lab);
+ }
+- return sym;
++ return function_symbol_result (sym, lab);
+ }
+
+ /* Find the number of a general purpose register in S. */
+@@ -13432,6 +13606,12 @@ sh_conditional_register_usage (void)
+ fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
+ call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
+ }
++ if (TARGET_FDPIC)
++ {
++ fixed_regs[PIC_REG] = 1;
++ call_used_regs[PIC_REG] = 1;
++ call_really_used_regs[PIC_REG] = 1;
++ }
+ /* Renesas saves and restores mac registers on call. */
+ if (TARGET_HITACHI && ! TARGET_NOMACSAVE)
+ {
+@@ -13460,14 +13640,32 @@ sh_conditional_register_usage (void)
+ static bool
+ sh_legitimate_constant_p (machine_mode mode, rtx x)
+ {
+- return (TARGET_SHMEDIA
+- ? ((mode != DFmode && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
+- || x == CONST0_RTX (mode)
+- || !TARGET_SHMEDIA_FPU
+- || TARGET_SHMEDIA64)
+- : (GET_CODE (x) != CONST_DOUBLE
+- || mode == DFmode || mode == SFmode
+- || mode == DImode || GET_MODE (x) == VOIDmode));
++ if (SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P)
++ {
++ rtx base, offset;
++ split_const (x, &base, &offset);
++
++ if (GET_CODE (base) == SYMBOL_REF
++ && !offset_within_block_p (base, INTVAL (offset)))
++ return false;
++ }
++
++ if (TARGET_FDPIC
++ && (SYMBOLIC_CONST_P (x)
++ || (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
++ && SYMBOLIC_CONST_P (XEXP (XEXP (x, 0), 0)))))
++ return false;
++
++ if (TARGET_SHMEDIA
++ && ((mode != DFmode && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
++ || x == CONST0_RTX (mode)
++ || !TARGET_SHMEDIA_FPU
++ || TARGET_SHMEDIA64))
++ return false;
++
++ return GET_CODE (x) != CONST_DOUBLE
++ || mode == DFmode || mode == SFmode
++ || mode == DImode || GET_MODE (x) == VOIDmode;
+ }
+
+ enum sh_divide_strategy_e sh_div_strategy = SH_DIV_STRATEGY_DEFAULT;
+@@ -14558,4 +14756,41 @@ sh_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size,
+ }
+ }
+
++bool
++sh_cannot_force_const_mem_p (machine_mode mode ATTRIBUTE_UNUSED,
++ rtx x ATTRIBUTE_UNUSED)
++{
++ return TARGET_FDPIC;
++}
++
++/* Emit insns to load the function address from FUNCDESC (an FDPIC
++ function descriptor) into r1 and the GOT address into r12,
++ returning an rtx for r1. */
++
++rtx
++sh_load_function_descriptor (rtx funcdesc)
++{
++ rtx r1 = gen_rtx_REG (Pmode, R1_REG);
++ rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
++ rtx fnaddr = gen_rtx_MEM (Pmode, funcdesc);
++ rtx gotaddr = gen_rtx_MEM (Pmode, plus_constant (Pmode, funcdesc, 4));
++
++ emit_move_insn (r1, fnaddr);
++ /* The ABI requires the entry point address to be loaded first, so
++ prevent the load from being moved after that of the GOT
++ address. */
++ emit_insn (gen_blockage ());
++ emit_move_insn (pic_reg, gotaddr);
++ return r1;
++}
++
++/* Return an rtx holding the initial value of the FDPIC register (the
++ FDPIC pointer passed in from the caller). */
++
++rtx
++sh_get_fdpic_reg_initial_val (void)
++{
++ return get_hard_reg_initial_val (Pmode, PIC_REG);
++}
++
+ #include "gt-sh.h"
+diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
+index aafcf28..e232179 100644
+--- a/gcc/config/sh/sh.h
++++ b/gcc/config/sh/sh.h
+@@ -321,7 +321,7 @@ extern int code_for_indirect_jump_scratch;
+ #endif
+
+ #ifndef SUBTARGET_ASM_SPEC
+-#define SUBTARGET_ASM_SPEC ""
++#define SUBTARGET_ASM_SPEC "%{mfdpic:--fdpic}"
+ #endif
+
+ #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
+@@ -349,7 +349,7 @@ extern int code_for_indirect_jump_scratch;
+ #define ASM_ISA_DEFAULT_SPEC ""
+ #endif /* MASK_SH5 */
+
+-#define SUBTARGET_LINK_EMUL_SUFFIX ""
++#define SUBTARGET_LINK_EMUL_SUFFIX "%{mfdpic:_fd}"
+ #define SUBTARGET_LINK_SPEC ""
+
+ /* Go via SH_LINK_SPEC to avoid code replication. */
+@@ -383,8 +383,18 @@ extern int code_for_indirect_jump_scratch;
+ "%{m2a*:%eSH2a does not support little-endian}}"
+ #endif
+
++#ifdef FDPIC_DEFAULT
++#define FDPIC_SELF_SPECS "%{!mno-fdpic:-mfdpic}"
++#else
++#define FDPIC_SELF_SPECS
++#endif
++
+ #undef DRIVER_SELF_SPECS
+-#define DRIVER_SELF_SPECS UNSUPPORTED_SH2A
++#define DRIVER_SELF_SPECS UNSUPPORTED_SH2A SUBTARGET_DRIVER_SELF_SPECS \
++ FDPIC_SELF_SPECS
++
++#undef SUBTARGET_DRIVER_SELF_SPECS
++#define SUBTARGET_DRIVER_SELF_SPECS
+
+ #define ASSEMBLER_DIALECT assembler_dialect
+
+@@ -942,6 +952,10 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
+ code access to data items. */
+ #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
+
++/* For FDPIC, the FDPIC register is call-clobbered (otherwise PLT
++ entries would need to handle saving and restoring it). */
++#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED TARGET_FDPIC
++
+ #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
+
+ /* Definitions for register eliminations.
+@@ -1566,7 +1580,8 @@ struct sh_args {
+ 6 000c 00000000 l2: .long function */
+
+ /* Length in units of the trampoline for entering a nested function. */
+-#define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
++#define TRAMPOLINE_SIZE \
++ (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : TARGET_FDPIC ? 32 : 16)
+
+ /* Alignment required for a trampoline in bits. */
+ #define TRAMPOLINE_ALIGNMENT \
+@@ -1622,6 +1637,10 @@ struct sh_args {
+ || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
+ : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
+
++/* True if SYMBOL + OFFSET constants must refer to something within
++ SYMBOL's section. */
++#define SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P TARGET_FDPIC
++
+ /* Maximum number of registers that can appear in a valid memory
+ address. */
+ #define MAX_REGS_PER_ADDRESS 2
+@@ -2262,9 +2281,11 @@ extern int current_function_interrupt;
+ /* We have to distinguish between code and data, so that we apply
+ datalabel where and only where appropriate. Use sdataN for data. */
+ #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
+- ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
+- | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr) \
+- | ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)))
++ ((TARGET_FDPIC \
++ ? ((GLOBAL) ? DW_EH_PE_indirect | DW_EH_PE_datarel : DW_EH_PE_pcrel) \
++ : ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
++ | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr))) \
++ | ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)))
+
+ /* Handle special EH pointer encodings. Absolute, pc-relative, and
+ indirect are handled automatically. */
+@@ -2277,6 +2298,17 @@ extern int current_function_interrupt;
+ SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
+ if (0) goto DONE; \
+ } \
++ if (TARGET_FDPIC \
++ && ((ENCODING) & 0xf0) == (DW_EH_PE_indirect | DW_EH_PE_datarel)) \
++ { \
++ fputs ("\t.ualong ", FILE); \
++ output_addr_const (FILE, ADDR); \
++ if (GET_CODE (ADDR) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (ADDR)) \
++ fputs ("@GOTFUNCDESC", FILE); \
++ else \
++ fputs ("@GOT", FILE); \
++ goto DONE; \
++ } \
+ } while (0)
+
+ #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
+diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md
+index d758e3b..45c9995 100644
+--- a/gcc/config/sh/sh.md
++++ b/gcc/config/sh/sh.md
+@@ -170,6 +170,9 @@ (define_c_enum "unspec" [
+ UNSPEC_SYMOFF
+ ;; (unspec [OFFSET ANCHOR] UNSPEC_PCREL_SYMOFF) == OFFSET - (ANCHOR - .).
+ UNSPEC_PCREL_SYMOFF
++ ;; For FDPIC
++ UNSPEC_GOTFUNCDESC
++ UNSPEC_GOTOFFFUNCDESC
+ ;; Misc builtins
+ UNSPEC_BUILTIN_STRLEN
+ ])
+@@ -2591,15 +2594,18 @@ (define_insn "udivsi3_sh2a"
+ ;; This reload would clobber the value in r0 we are trying to store.
+ ;; If we let reload allocate r0, then this problem can never happen.
+ (define_insn "udivsi3_i1"
+- [(set (match_operand:SI 0 "register_operand" "=z")
++ [(set (match_operand:SI 0 "register_operand" "=z,z")
+ (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
+ (clobber (reg:SI T_REG))
+ (clobber (reg:SI PR_REG))
+ (clobber (reg:SI R1_REG))
+ (clobber (reg:SI R4_REG))
+- (use (match_operand:SI 1 "arith_reg_operand" "r"))]
++ (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
++ (use (match_operand 2 "" "Z,Ccl"))]
+ "TARGET_SH1 && TARGET_DIVIDE_CALL_DIV1"
+- "jsr @%1%#"
++ "@
++ jsr @%1%#
++ bsrf %1\n%O2:%#"
+ [(set_attr "type" "sfunc")
+ (set_attr "needs_delay_slot" "yes")])
+
+@@ -2648,7 +2654,7 @@ (define_expand "udivsi3_i4_media"
+ })
+
+ (define_insn "udivsi3_i4"
+- [(set (match_operand:SI 0 "register_operand" "=y")
++ [(set (match_operand:SI 0 "register_operand" "=y,y")
+ (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
+ (clobber (reg:SI T_REG))
+ (clobber (reg:SI PR_REG))
+@@ -2660,16 +2666,19 @@ (define_insn "udivsi3_i4"
+ (clobber (reg:SI R4_REG))
+ (clobber (reg:SI R5_REG))
+ (clobber (reg:SI FPSCR_STAT_REG))
+- (use (match_operand:SI 1 "arith_reg_operand" "r"))
++ (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
++ (use (match_operand 2 "" "Z,Ccl"))
+ (use (reg:SI FPSCR_MODES_REG))]
+ "TARGET_FPU_DOUBLE && ! TARGET_FPU_SINGLE"
+- "jsr @%1%#"
++ "@
++ jsr @%1%#
++ bsrf %1\n%O2:%#"
+ [(set_attr "type" "sfunc")
+ (set_attr "fp_mode" "double")
+ (set_attr "needs_delay_slot" "yes")])
+
+ (define_insn "udivsi3_i4_single"
+- [(set (match_operand:SI 0 "register_operand" "=y")
++ [(set (match_operand:SI 0 "register_operand" "=y,y")
+ (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
+ (clobber (reg:SI T_REG))
+ (clobber (reg:SI PR_REG))
+@@ -2680,10 +2689,13 @@ (define_insn "udivsi3_i4_single"
+ (clobber (reg:SI R1_REG))
+ (clobber (reg:SI R4_REG))
+ (clobber (reg:SI R5_REG))
+- (use (match_operand:SI 1 "arith_reg_operand" "r"))]
++ (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
++ (use (match_operand 2 "" "Z,Ccl"))]
+ "(TARGET_FPU_SINGLE_ONLY || TARGET_FPU_DOUBLE || TARGET_SHCOMPACT)
+ && TARGET_FPU_SINGLE"
+- "jsr @%1%#"
++ "@
++ jsr @%1%#
++ bsrf %1\n%O2:%#"
+ [(set_attr "type" "sfunc")
+ (set_attr "needs_delay_slot" "yes")])
+
+@@ -2742,11 +2754,11 @@ (define_expand "udivsi3"
+ }
+ else if (TARGET_DIVIDE_CALL_FP)
+ {
+- function_symbol (operands[3], "__udivsi3_i4", SFUNC_STATIC);
++ rtx lab = function_symbol (operands[3], "__udivsi3_i4", SFUNC_STATIC).lab;
+ if (TARGET_FPU_SINGLE)
+- last = gen_udivsi3_i4_single (operands[0], operands[3]);
++ last = gen_udivsi3_i4_single (operands[0], operands[3], lab);
+ else
+- last = gen_udivsi3_i4 (operands[0], operands[3]);
++ last = gen_udivsi3_i4 (operands[0], operands[3], lab);
+ }
+ else if (TARGET_SHMEDIA_FPU)
+ {
+@@ -2771,14 +2783,14 @@ (define_expand "udivsi3"
+ if (TARGET_SHMEDIA)
+ last = gen_udivsi3_i1_media (operands[0], operands[3]);
+ else if (TARGET_FPU_ANY)
+- last = gen_udivsi3_i4_single (operands[0], operands[3]);
++ last = gen_udivsi3_i4_single (operands[0], operands[3], const0_rtx);
+ else
+- last = gen_udivsi3_i1 (operands[0], operands[3]);
++ last = gen_udivsi3_i1 (operands[0], operands[3], const0_rtx);
+ }
+ else
+ {
+- function_symbol (operands[3], "__udivsi3", SFUNC_STATIC);
+- last = gen_udivsi3_i1 (operands[0], operands[3]);
++ rtx lab = function_symbol (operands[3], "__udivsi3", SFUNC_STATIC).lab;
++ last = gen_udivsi3_i1 (operands[0], operands[3], lab);
+ }
+ emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
+ emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
+@@ -2906,7 +2918,7 @@ (define_insn_and_split "*divsi_inv_call_combine"
+ emit_move_insn (gen_rtx_REG (DImode, R20_REG), x);
+ break;
+ }
+- sym = function_symbol (NULL, name, kind);
++ sym = function_symbol (NULL, name, kind).sym;
+ emit_insn (gen_divsi3_media_2 (operands[0], sym));
+ DONE;
+ }
+@@ -2926,31 +2938,37 @@ (define_expand "divsi3_i4_media"
+ })
+
+ (define_insn "divsi3_i4"
+- [(set (match_operand:SI 0 "register_operand" "=y")
++ [(set (match_operand:SI 0 "register_operand" "=y,y")
+ (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
+ (clobber (reg:SI PR_REG))
+ (clobber (reg:DF DR0_REG))
+ (clobber (reg:DF DR2_REG))
+ (clobber (reg:SI FPSCR_STAT_REG))
+- (use (match_operand:SI 1 "arith_reg_operand" "r"))
++ (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
++ (use (match_operand 2 "" "Z,Ccl"))
+ (use (reg:SI FPSCR_MODES_REG))]
+ "TARGET_FPU_DOUBLE && ! TARGET_FPU_SINGLE"
+- "jsr @%1%#"
++ "@
++ jsr @%1%#
++ bsrf %1\n%O2:%#"
+ [(set_attr "type" "sfunc")
+ (set_attr "fp_mode" "double")
+ (set_attr "needs_delay_slot" "yes")])
+
+ (define_insn "divsi3_i4_single"
+- [(set (match_operand:SI 0 "register_operand" "=y")
++ [(set (match_operand:SI 0 "register_operand" "=y,y")
+ (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
+ (clobber (reg:SI PR_REG))
+ (clobber (reg:DF DR0_REG))
+ (clobber (reg:DF DR2_REG))
+ (clobber (reg:SI R2_REG))
+- (use (match_operand:SI 1 "arith_reg_operand" "r"))]
++ (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
++ (use (match_operand 2 "" "Z,Ccl"))]
+ "(TARGET_FPU_SINGLE_ONLY || TARGET_FPU_DOUBLE || TARGET_SHCOMPACT)
+ && TARGET_FPU_SINGLE"
+- "jsr @%1%#"
++ "@
++ jsr @%1%#
++ bsrf %1\n%O2:%#"
+ [(set_attr "type" "sfunc")
+ (set_attr "needs_delay_slot" "yes")])
+
+@@ -2994,11 +3012,12 @@ (define_expand "divsi3"
+ }
+ else if (TARGET_DIVIDE_CALL_FP)
+ {
+- function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_STATIC);
++ rtx lab = function_symbol (operands[3], sh_divsi3_libfunc,
++ SFUNC_STATIC).lab;
+ if (TARGET_FPU_SINGLE)
+- last = gen_divsi3_i4_single (operands[0], operands[3]);
++ last = gen_divsi3_i4_single (operands[0], operands[3], lab);
+ else
+- last = gen_divsi3_i4 (operands[0], operands[3]);
++ last = gen_divsi3_i4 (operands[0], operands[3], lab);
+ }
+ else if (TARGET_SH2A)
+ {
+@@ -3113,7 +3132,7 @@ (define_expand "divsi3"
+ last = ((TARGET_DIVIDE_CALL2 ? gen_divsi3_media_2 : gen_divsi3_i1_media)
+ (operands[0], operands[3]));
+ else if (TARGET_FPU_ANY)
+- last = gen_divsi3_i4_single (operands[0], operands[3]);
++ last = gen_divsi3_i4_single (operands[0], operands[3], const0_rtx);
+ else
+ last = gen_divsi3_i1 (operands[0], operands[3]);
+ }
+@@ -3713,7 +3732,7 @@ (define_expand "mulsi3"
+ {
+ /* The address must be set outside the libcall,
+ since it goes into a pseudo. */
+- rtx sym = function_symbol (NULL, "__mulsi3", SFUNC_STATIC);
++ rtx sym = function_symbol (NULL, "__mulsi3", SFUNC_STATIC).sym;
+ rtx addr = force_reg (SImode, sym);
+ rtx insns = gen_mulsi3_call (operands[0], operands[1],
+ operands[2], addr);
+@@ -4970,8 +4989,8 @@ (define_expand "ashlsi3"
+ {
+ emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
+ rtx funcaddr = gen_reg_rtx (Pmode);
+- function_symbol (funcaddr, "__ashlsi3_r0", SFUNC_STATIC);
+- emit_insn (gen_ashlsi3_d_call (operands[0], operands[2], funcaddr));
++ rtx lab = function_symbol (funcaddr, "__ashlsi3_r0", SFUNC_STATIC).lab;
++ emit_insn (gen_ashlsi3_d_call (operands[0], operands[2], funcaddr, lab));
+
+ DONE;
+ }
+@@ -5024,15 +5043,18 @@ (define_insn_and_split "ashlsi3_d"
+ ;; In order to make combine understand the truncation of the shift amount
+ ;; operand we have to allow it to use pseudo regs for the shift operands.
+ (define_insn "ashlsi3_d_call"
+- [(set (match_operand:SI 0 "arith_reg_dest" "=z")
++ [(set (match_operand:SI 0 "arith_reg_dest" "=z,z")
+ (ashift:SI (reg:SI R4_REG)
+- (and:SI (match_operand:SI 1 "arith_reg_operand" "z")
++ (and:SI (match_operand:SI 1 "arith_reg_operand" "z,z")
+ (const_int 31))))
+- (use (match_operand:SI 2 "arith_reg_operand" "r"))
++ (use (match_operand:SI 2 "arith_reg_operand" "r,r"))
++ (use (match_operand 3 "" "Z,Ccl"))
+ (clobber (reg:SI T_REG))
+ (clobber (reg:SI PR_REG))]
+ "TARGET_SH1 && !TARGET_DYNSHIFT"
+- "jsr @%2%#"
++ "@
++ jsr @%2%#
++ bsrf %2\n%O3:%#"
+ [(set_attr "type" "sfunc")
+ (set_attr "needs_delay_slot" "yes")])
+
+@@ -5374,12 +5396,15 @@ (define_insn "ashrsi3_d"
+ (define_insn "ashrsi3_n"
+ [(set (reg:SI R4_REG)
+ (ashiftrt:SI (reg:SI R4_REG)
+- (match_operand:SI 0 "const_int_operand" "i")))
++ (match_operand:SI 0 "const_int_operand" "i,i")))
+ (clobber (reg:SI T_REG))
+ (clobber (reg:SI PR_REG))
+- (use (match_operand:SI 1 "arith_reg_operand" "r"))]
++ (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
++ (use (match_operand 2 "" "Z,Ccl"))]
+ "TARGET_SH1"
+- "jsr @%1%#"
++ "@
++ jsr @%1%#
++ bsrf %1\n%O2:%#"
+ [(set_attr "type" "sfunc")
+ (set_attr "needs_delay_slot" "yes")])
+
+@@ -5532,8 +5557,8 @@ (define_expand "lshrsi3"
+ {
+ emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
+ rtx funcaddr = gen_reg_rtx (Pmode);
+- function_symbol (funcaddr, "__lshrsi3_r0", SFUNC_STATIC);
+- emit_insn (gen_lshrsi3_d_call (operands[0], operands[2], funcaddr));
++ rtx lab = function_symbol (funcaddr, "__lshrsi3_r0", SFUNC_STATIC).lab;
++ emit_insn (gen_lshrsi3_d_call (operands[0], operands[2], funcaddr, lab));
+ DONE;
+ }
+ })
+@@ -5585,15 +5610,18 @@ (define_insn_and_split "lshrsi3_d"
+ ;; In order to make combine understand the truncation of the shift amount
+ ;; operand we have to allow it to use pseudo regs for the shift operands.
+ (define_insn "lshrsi3_d_call"
+- [(set (match_operand:SI 0 "arith_reg_dest" "=z")
++ [(set (match_operand:SI 0 "arith_reg_dest" "=z,z")
+ (lshiftrt:SI (reg:SI R4_REG)
+- (and:SI (match_operand:SI 1 "arith_reg_operand" "z")
++ (and:SI (match_operand:SI 1 "arith_reg_operand" "z,z")
+ (const_int 31))))
+- (use (match_operand:SI 2 "arith_reg_operand" "r"))
++ (use (match_operand:SI 2 "arith_reg_operand" "r,r"))
++ (use (match_operand 3 "" "Z,Ccl"))
+ (clobber (reg:SI T_REG))
+ (clobber (reg:SI PR_REG))]
+ "TARGET_SH1 && !TARGET_DYNSHIFT"
+- "jsr @%2%#"
++ "@
++ jsr @%2%#
++ bsrf %2\n%O3:%#"
+ [(set_attr "type" "sfunc")
+ (set_attr "needs_delay_slot" "yes")])
+
+@@ -7315,7 +7343,7 @@ (define_expand "ic_invalidate_line"
+ }
+ else if (TARGET_SHCOMPACT)
+ {
+- operands[1] = function_symbol (NULL, "__ic_invalidate", SFUNC_STATIC);
++ operands[1] = function_symbol (NULL, "__ic_invalidate", SFUNC_STATIC).sym;
+ operands[1] = force_reg (Pmode, operands[1]);
+ emit_insn (gen_ic_invalidate_line_compact (operands[0], operands[1]));
+ DONE;
+@@ -7397,7 +7425,7 @@ (define_expand "initialize_trampoline"
+
+ tramp = force_reg (Pmode, operands[0]);
+ sfun = force_reg (Pmode, function_symbol (NULL, "__init_trampoline",
+- SFUNC_STATIC));
++ SFUNC_STATIC).sym);
+ emit_move_insn (gen_rtx_REG (SImode, R2_REG), operands[1]);
+ emit_move_insn (gen_rtx_REG (SImode, R3_REG), operands[2]);
+
+@@ -9459,9 +9487,29 @@ (define_insn "calli"
+ (match_operand 1 "" ""))
+ (use (reg:SI FPSCR_MODES_REG))
+ (clobber (reg:SI PR_REG))]
+- "TARGET_SH1"
++ "TARGET_SH1 && !TARGET_FDPIC"
+ {
+- if (TARGET_SH2A && (dbr_sequence_length () == 0))
++ if (TARGET_SH2A && dbr_sequence_length () == 0)
++ return "jsr/n @%0";
++ else
++ return "jsr @%0%#";
++}
++ [(set_attr "type" "call")
++ (set (attr "fp_mode")
++ (if_then_else (eq_attr "fpu_single" "yes")
++ (const_string "single") (const_string "double")))
++ (set_attr "needs_delay_slot" "yes")
++ (set_attr "fp_set" "unknown")])
++
++(define_insn "calli_fdpic"
++ [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
++ (match_operand 1))
++ (use (reg:SI FPSCR_MODES_REG))
++ (use (reg:SI PIC_REG))
++ (clobber (reg:SI PR_REG))]
++ "TARGET_FDPIC"
++{
++ if (TARGET_SH2A && dbr_sequence_length () == 0)
+ return "jsr/n @%0";
+ else
+ return "jsr @%0%#";
+@@ -9588,9 +9636,30 @@ (define_insn "call_valuei"
+ (match_operand 2 "" "")))
+ (use (reg:SI FPSCR_MODES_REG))
+ (clobber (reg:SI PR_REG))]
+- "TARGET_SH1"
++ "TARGET_SH1 && !TARGET_FDPIC"
++{
++ if (TARGET_SH2A && dbr_sequence_length () == 0)
++ return "jsr/n @%1";
++ else
++ return "jsr @%1%#";
++}
++ [(set_attr "type" "call")
++ (set (attr "fp_mode")
++ (if_then_else (eq_attr "fpu_single" "yes")
++ (const_string "single") (const_string "double")))
++ (set_attr "needs_delay_slot" "yes")
++ (set_attr "fp_set" "unknown")])
++
++(define_insn "call_valuei_fdpic"
++ [(set (match_operand 0 "" "=rf")
++ (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
++ (match_operand 2)))
++ (use (reg:SI FPSCR_REG))
++ (use (reg:SI PIC_REG))
++ (clobber (reg:SI PR_REG))]
++ "TARGET_FDPIC"
+ {
+- if (TARGET_SH2A && (dbr_sequence_length () == 0))
++ if (TARGET_SH2A && dbr_sequence_length () == 0)
+ return "jsr/n @%1";
+ else
+ return "jsr @%1%#";
+@@ -9725,6 +9794,12 @@ (define_expand "call"
+ (clobber (reg:SI PR_REG))])]
+ ""
+ {
++ if (TARGET_FDPIC)
++ {
++ rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
++ emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ());
++ }
++
+ if (TARGET_SHMEDIA)
+ {
+ operands[0] = shmedia_prepare_call_address (operands[0], 0);
+@@ -9759,8 +9834,8 @@ (define_expand "call"
+ run out of registers when adjusting fpscr for the call. */
+ emit_insn (gen_force_mode_for_call ());
+
+- operands[0]
+- = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT);
++ operands[0] = function_symbol (NULL, "__GCC_shcompact_call_trampoline",
++ SFUNC_GOT).sym;
+ operands[0] = force_reg (SImode, operands[0]);
+
+ emit_move_insn (r0, func);
+@@ -9808,7 +9883,13 @@ (define_expand "call"
+ operands[1] = operands[2];
+ }
+
+- emit_call_insn (gen_calli (operands[0], operands[1]));
++ if (TARGET_FDPIC)
++ {
++ operands[0] = sh_load_function_descriptor (operands[0]);
++ emit_call_insn (gen_calli_fdpic (operands[0], operands[1]));
++ }
++ else
++ emit_call_insn (gen_calli (operands[0], operands[1]));
+ DONE;
+ })
+
+@@ -9888,7 +9969,7 @@ (define_expand "call_pop"
+ emit_insn (gen_force_mode_for_call ());
+
+ operands[0] = function_symbol (NULL, "__GCC_shcompact_call_trampoline",
+- SFUNC_GOT);
++ SFUNC_GOT).sym;
+ operands[0] = force_reg (SImode, operands[0]);
+
+ emit_move_insn (r0, func);
+@@ -9913,6 +9994,12 @@ (define_expand "call_value"
+ (clobber (reg:SI PR_REG))])]
+ ""
+ {
++ if (TARGET_FDPIC)
++ {
++ rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
++ emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ());
++ }
++
+ if (TARGET_SHMEDIA)
+ {
+ operands[1] = shmedia_prepare_call_address (operands[1], 0);
+@@ -9948,8 +10035,8 @@ (define_expand "call_value"
+ run out of registers when adjusting fpscr for the call. */
+ emit_insn (gen_force_mode_for_call ());
+
+- operands[1]
+- = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT);
++ operands[1] = function_symbol (NULL, "__GCC_shcompact_call_trampoline",
++ SFUNC_GOT).sym;
+ operands[1] = force_reg (SImode, operands[1]);
+
+ emit_move_insn (r0, func);
+@@ -9997,7 +10084,14 @@ (define_expand "call_value"
+ else
+ operands[1] = force_reg (SImode, XEXP (operands[1], 0));
+
+- emit_call_insn (gen_call_valuei (operands[0], operands[1], operands[2]));
++ if (TARGET_FDPIC)
++ {
++ operands[1] = sh_load_function_descriptor (operands[1]);
++ emit_call_insn (gen_call_valuei_fdpic (operands[0], operands[1],
++ operands[2]));
++ }
++ else
++ emit_call_insn (gen_call_valuei (operands[0], operands[1], operands[2]));
+ DONE;
+ })
+
+@@ -10006,7 +10100,21 @@ (define_insn "sibcalli"
+ (match_operand 1 "" ""))
+ (use (reg:SI FPSCR_MODES_REG))
+ (return)]
+- "TARGET_SH1"
++ "TARGET_SH1 && !TARGET_FDPIC"
++ "jmp @%0%#"
++ [(set_attr "needs_delay_slot" "yes")
++ (set (attr "fp_mode")
++ (if_then_else (eq_attr "fpu_single" "yes")
++ (const_string "single") (const_string "double")))
++ (set_attr "type" "jump_ind")])
++
++(define_insn "sibcalli_fdpic"
++ [(call (mem:SI (match_operand:SI 0 "register_operand" "k"))
++ (match_operand 1))
++ (use (reg:SI FPSCR_MODES_REG))
++ (use (reg:SI PIC_REG))
++ (return)]
++ "TARGET_FDPIC"
+ "jmp @%0%#"
+ [(set_attr "needs_delay_slot" "yes")
+ (set (attr "fp_mode")
+@@ -10020,7 +10128,25 @@ (define_insn "sibcalli_pcrel"
+ (use (match_operand 2 "" ""))
+ (use (reg:SI FPSCR_MODES_REG))
+ (return)]
+- "TARGET_SH2"
++ "TARGET_SH2 && !TARGET_FDPIC"
++{
++ return "braf %0" "\n"
++ "%O2:%#";
++}
++ [(set_attr "needs_delay_slot" "yes")
++ (set (attr "fp_mode")
++ (if_then_else (eq_attr "fpu_single" "yes")
++ (const_string "single") (const_string "double")))
++ (set_attr "type" "jump_ind")])
++
++(define_insn "sibcalli_pcrel_fdpic"
++ [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "k"))
++ (match_operand 1))
++ (use (match_operand 2))
++ (use (reg:SI FPSCR_MODES_REG))
++ (use (reg:SI PIC_REG))
++ (return)]
++ "TARGET_SH2 && TARGET_FDPIC"
+ {
+ return "braf %0" "\n"
+ "%O2:%#";
+@@ -10053,7 +10179,7 @@ (define_insn_and_split "sibcall_pcrel"
+ (use (reg:SI FPSCR_MODES_REG))
+ (clobber (match_scratch:SI 2 "=&k"))
+ (return)]
+- "TARGET_SH2"
++ "TARGET_SH2 && !TARGET_FDPIC"
+ "#"
+ "reload_completed"
+ [(const_int 0)]
+@@ -10073,6 +10199,32 @@ (define_insn_and_split "sibcall_pcrel"
+ (const_string "single") (const_string "double")))
+ (set_attr "type" "jump_ind")])
+
++(define_insn_and_split "sibcall_pcrel_fdpic"
++ [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand"))
++ (match_operand 1))
++ (use (reg:SI FPSCR_MODES_REG))
++ (use (reg:SI PIC_REG))
++ (clobber (match_scratch:SI 2 "=k"))
++ (return)]
++ "TARGET_SH2 && TARGET_FDPIC"
++ "#"
++ "&& reload_completed"
++ [(const_int 0)]
++{
++ rtx lab = PATTERN (gen_call_site ());
++
++ sh_expand_sym_label2reg (operands[2], operands[0], lab, true);
++ rtx i = emit_call_insn (gen_sibcalli_pcrel_fdpic (operands[2], operands[1],
++ copy_rtx (lab)));
++ SIBLING_CALL_P (i) = 1;
++ DONE;
++}
++ [(set_attr "needs_delay_slot" "yes")
++ (set (attr "fp_mode")
++ (if_then_else (eq_attr "fpu_single" "yes")
++ (const_string "single") (const_string "double")))
++ (set_attr "type" "jump_ind")])
++
+ (define_insn "sibcall_compact"
+ [(call (mem:SI (match_operand:SI 0 "register_operand" "k,k"))
+ (match_operand 1 "" ""))
+@@ -10117,6 +10269,12 @@ (define_expand "sibcall"
+ (return)])]
+ ""
+ {
++ if (TARGET_FDPIC)
++ {
++ rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
++ emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ());
++ }
++
+ if (TARGET_SHMEDIA)
+ {
+ operands[0] = shmedia_prepare_call_address (operands[0], 1);
+@@ -10161,8 +10319,8 @@ (define_expand "sibcall"
+ run out of registers when adjusting fpscr for the call. */
+ emit_insn (gen_force_mode_for_call ());
+
+- operands[0]
+- = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT);
++ operands[0] = function_symbol (NULL, "__GCC_shcompact_call_trampoline",
++ SFUNC_GOT).sym;
+ operands[0] = force_reg (SImode, operands[0]);
+
+ /* We don't need a return trampoline, since the callee will
+@@ -10196,13 +10354,23 @@ (define_expand "sibcall"
+ static functions. */
+ && SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
+ {
+- emit_call_insn (gen_sibcall_pcrel (XEXP (operands[0], 0), operands[1]));
++ if (TARGET_FDPIC)
++ emit_call_insn (gen_sibcall_pcrel_fdpic (XEXP (operands[0], 0),
++ operands[1]));
++ else
++ emit_call_insn (gen_sibcall_pcrel (XEXP (operands[0], 0), operands[1]));
+ DONE;
+ }
+ else
+ operands[0] = force_reg (SImode, XEXP (operands[0], 0));
+
+- emit_call_insn (gen_sibcalli (operands[0], operands[1]));
++ if (TARGET_FDPIC)
++ {
++ operands[0] = sh_load_function_descriptor (operands[0]);
++ emit_call_insn (gen_sibcalli_fdpic (operands[0], operands[1]));
++ }
++ else
++ emit_call_insn (gen_sibcalli (operands[0], operands[1]));
+ DONE;
+ })
+
+@@ -10212,7 +10380,22 @@ (define_insn "sibcall_valuei"
+ (match_operand 2 "" "")))
+ (use (reg:SI FPSCR_MODES_REG))
+ (return)]
+- "TARGET_SH1"
++ "TARGET_SH1 && !TARGET_FDPIC"
++ "jmp @%1%#"
++ [(set_attr "needs_delay_slot" "yes")
++ (set (attr "fp_mode")
++ (if_then_else (eq_attr "fpu_single" "yes")
++ (const_string "single") (const_string "double")))
++ (set_attr "type" "jump_ind")])
++
++(define_insn "sibcall_valuei_fdpic"
++ [(set (match_operand 0 "" "=rf")
++ (call (mem:SI (match_operand:SI 1 "register_operand" "k"))
++ (match_operand 2)))
++ (use (reg:SI FPSCR_MODES_REG))
++ (use (reg:SI PIC_REG))
++ (return)]
++ "TARGET_FDPIC"
+ "jmp @%1%#"
+ [(set_attr "needs_delay_slot" "yes")
+ (set (attr "fp_mode")
+@@ -10227,7 +10410,26 @@ (define_insn "sibcall_valuei_pcrel"
+ (use (match_operand 3 "" ""))
+ (use (reg:SI FPSCR_MODES_REG))
+ (return)]
+- "TARGET_SH2"
++ "TARGET_SH2 && !TARGET_FDPIC"
++{
++ return "braf %1" "\n"
++ "%O3:%#";
++}
++ [(set_attr "needs_delay_slot" "yes")
++ (set (attr "fp_mode")
++ (if_then_else (eq_attr "fpu_single" "yes")
++ (const_string "single") (const_string "double")))
++ (set_attr "type" "jump_ind")])
++
++(define_insn "sibcall_valuei_pcrel_fdpic"
++ [(set (match_operand 0 "" "=rf")
++ (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "k"))
++ (match_operand 2)))
++ (use (match_operand 3))
++ (use (reg:SI FPSCR_MODES_REG))
++ (use (reg:SI PIC_REG))
++ (return)]
++ "TARGET_SH2 && TARGET_FDPIC"
+ {
+ return "braf %1" "\n"
+ "%O3:%#";
+@@ -10245,7 +10447,7 @@ (define_insn_and_split "sibcall_value_pcrel"
+ (use (reg:SI FPSCR_MODES_REG))
+ (clobber (match_scratch:SI 3 "=&k"))
+ (return)]
+- "TARGET_SH2"
++ "TARGET_SH2 && !TARGET_FDPIC"
+ "#"
+ "reload_completed"
+ [(const_int 0)]
+@@ -10267,6 +10469,35 @@ (define_insn_and_split "sibcall_value_pcrel"
+ (const_string "single") (const_string "double")))
+ (set_attr "type" "jump_ind")])
+
++(define_insn_and_split "sibcall_value_pcrel_fdpic"
++ [(set (match_operand 0 "" "=rf")
++ (call (mem:SI (match_operand:SI 1 "symbol_ref_operand"))
++ (match_operand 2)))
++ (use (reg:SI FPSCR_MODES_REG))
++ (use (reg:SI PIC_REG))
++ (clobber (match_scratch:SI 3 "=k"))
++ (return)]
++ "TARGET_SH2 && TARGET_FDPIC"
++ "#"
++ "&& reload_completed"
++ [(const_int 0)]
++{
++ rtx lab = PATTERN (gen_call_site ());
++
++ sh_expand_sym_label2reg (operands[3], operands[1], lab, true);
++ rtx i = emit_call_insn (gen_sibcall_valuei_pcrel_fdpic (operands[0],
++ operands[3],
++ operands[2],
++ copy_rtx (lab)));
++ SIBLING_CALL_P (i) = 1;
++ DONE;
++}
++ [(set_attr "needs_delay_slot" "yes")
++ (set (attr "fp_mode")
++ (if_then_else (eq_attr "fpu_single" "yes")
++ (const_string "single") (const_string "double")))
++ (set_attr "type" "jump_ind")])
++
+ (define_insn "sibcall_value_compact"
+ [(set (match_operand 0 "" "=rf,rf")
+ (call (mem:SI (match_operand:SI 1 "register_operand" "k,k"))
+@@ -10314,6 +10545,12 @@ (define_expand "sibcall_value"
+ (return)])]
+ ""
+ {
++ if (TARGET_FDPIC)
++ {
++ rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
++ emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ());
++ }
++
+ if (TARGET_SHMEDIA)
+ {
+ operands[1] = shmedia_prepare_call_address (operands[1], 1);
+@@ -10359,8 +10596,8 @@ (define_expand "sibcall_value"
+ run out of registers when adjusting fpscr for the call. */
+ emit_insn (gen_force_mode_for_call ());
+
+- operands[1]
+- = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT);
++ operands[1] = function_symbol (NULL, "__GCC_shcompact_call_trampoline",
++ SFUNC_GOT).sym;
+ operands[1] = force_reg (SImode, operands[1]);
+
+ /* We don't need a return trampoline, since the callee will
+@@ -10395,15 +10632,27 @@ (define_expand "sibcall_value"
+ static functions. */
+ && SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0)))
+ {
+- emit_call_insn (gen_sibcall_value_pcrel (operands[0],
+- XEXP (operands[1], 0),
+- operands[2]));
++ if (TARGET_FDPIC)
++ emit_call_insn (gen_sibcall_value_pcrel_fdpic (operands[0],
++ XEXP (operands[1], 0),
++ operands[2]));
++ else
++ emit_call_insn (gen_sibcall_value_pcrel (operands[0],
++ XEXP (operands[1], 0),
++ operands[2]));
+ DONE;
+ }
+ else
+ operands[1] = force_reg (SImode, XEXP (operands[1], 0));
+
+- emit_call_insn (gen_sibcall_valuei (operands[0], operands[1], operands[2]));
++ if (TARGET_FDPIC)
++ {
++ operands[1] = sh_load_function_descriptor (operands[1]);
++ emit_call_insn (gen_sibcall_valuei_fdpic (operands[0], operands[1],
++ operands[2]));
++ }
++ else
++ emit_call_insn (gen_sibcall_valuei (operands[0], operands[1], operands[2]));
+ DONE;
+ })
+
+@@ -10487,7 +10736,7 @@ (define_expand "call_value_pop"
+ emit_insn (gen_force_mode_for_call ());
+
+ operands[1] = function_symbol (NULL, "__GCC_shcompact_call_trampoline",
+- SFUNC_GOT);
++ SFUNC_GOT).sym;
+ operands[1] = force_reg (SImode, operands[1]);
+
+ emit_move_insn (r0, func);
+@@ -10685,6 +10934,13 @@ (define_expand "GOTaddr2picreg"
+ DONE;
+ }
+
++ if (TARGET_FDPIC)
++ {
++ rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
++ emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ());
++ DONE;
++ }
++
+ operands[1] = gen_rtx_REG (Pmode, PIC_REG);
+ operands[2] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
+
+@@ -10820,10 +11076,13 @@ (define_expand "symGOT_load"
+ rtx mem;
+ bool stack_chk_guard_p = false;
+
++ rtx picreg = TARGET_FDPIC ? sh_get_fdpic_reg_initial_val ()
++ : gen_rtx_REG (Pmode, PIC_REG);
++
+ operands[2] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
+ operands[3] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
+
+- if (!TARGET_SHMEDIA
++ if (!TARGET_SHMEDIA && !TARGET_FDPIC
+ && flag_stack_protect
+ && GET_CODE (operands[1]) == CONST
+ && GET_CODE (XEXP (operands[1], 0)) == UNSPEC
+@@ -10862,8 +11121,7 @@ (define_expand "symGOT_load"
+ if (stack_chk_guard_p)
+ emit_insn (gen_chk_guard_add (operands[3], operands[2]));
+ else
+- emit_move_insn (operands[3], gen_rtx_PLUS (Pmode, operands[2],
+- gen_rtx_REG (Pmode, PIC_REG)));
++ emit_move_insn (operands[3], gen_rtx_PLUS (Pmode, operands[2], picreg));
+
+ /* N.B. This is not constant for a GOTPLT relocation. */
+ mem = gen_rtx_MEM (Pmode, operands[3]);
+@@ -10894,6 +11152,23 @@ (define_expand "symGOT2reg"
+ DONE;
+ })
+
++(define_expand "sym2GOTFUNCDESC"
++ [(const (unspec [(match_operand 0)] UNSPEC_GOTFUNCDESC))]
++ "TARGET_FDPIC")
++
++(define_expand "symGOTFUNCDESC2reg"
++ [(match_operand 0) (match_operand 1)]
++ "TARGET_FDPIC"
++{
++ rtx gotsym = gen_sym2GOTFUNCDESC (operands[1]);
++ PUT_MODE (gotsym, Pmode);
++ rtx insn = emit_insn (gen_symGOT_load (operands[0], gotsym));
++
++ MEM_READONLY_P (SET_SRC (PATTERN (insn))) = 1;
++
++ DONE;
++})
++
+ (define_expand "symGOTPLT2reg"
+ [(match_operand 0 "" "") (match_operand 1 "" "")]
+ ""
+@@ -10920,18 +11195,39 @@ (define_expand "symGOTOFF2reg"
+ ? operands[0]
+ : gen_reg_rtx (GET_MODE (operands[0])));
+
++ rtx picreg = TARGET_FDPIC ? sh_get_fdpic_reg_initial_val ()
++ : gen_rtx_REG (Pmode, PIC_REG);
++
+ gotoffsym = gen_sym2GOTOFF (operands[1]);
+ PUT_MODE (gotoffsym, Pmode);
+ emit_move_insn (t, gotoffsym);
+- insn = emit_move_insn (operands[0],
+- gen_rtx_PLUS (Pmode, t,
+- gen_rtx_REG (Pmode, PIC_REG)));
++ insn = emit_move_insn (operands[0], gen_rtx_PLUS (Pmode, t, picreg));
+
+ set_unique_reg_note (insn, REG_EQUAL, operands[1]);
+
+ DONE;
+ })
+
++(define_expand "sym2GOTOFFFUNCDESC"
++ [(const (unspec [(match_operand 0)] UNSPEC_GOTOFFFUNCDESC))]
++ "TARGET_FDPIC")
++
++(define_expand "symGOTOFFFUNCDESC2reg"
++ [(match_operand 0) (match_operand 1)]
++ "TARGET_FDPIC"
++{
++ rtx picreg = sh_get_fdpic_reg_initial_val ();
++ rtx t = !can_create_pseudo_p ()
++ ? operands[0]
++ : gen_reg_rtx (GET_MODE (operands[0]));
++
++ rtx gotoffsym = gen_sym2GOTOFFFUNCDESC (operands[1]);
++ PUT_MODE (gotoffsym, Pmode);
++ emit_move_insn (t, gotoffsym);
++ emit_move_insn (operands[0], gen_rtx_PLUS (Pmode, t, picreg));
++ DONE;
++})
++
+ (define_expand "symPLT_label2reg"
+ [(set (match_operand:SI 0 "" "")
+ (const:SI
+@@ -12688,18 +12984,22 @@ (define_expand "movmemsi"
+ (define_insn "block_move_real"
+ [(parallel [(set (mem:BLK (reg:SI R4_REG))
+ (mem:BLK (reg:SI R5_REG)))
+- (use (match_operand:SI 0 "arith_reg_operand" "r"))
++ (use (match_operand:SI 0 "arith_reg_operand" "r,r"))
++ (use (match_operand 1 "" "Z,Ccl"))
+ (clobber (reg:SI PR_REG))
+ (clobber (reg:SI R0_REG))])]
+ "TARGET_SH1 && ! TARGET_HARD_SH4"
+- "jsr @%0%#"
++ "@
++ jsr @%0%#
++ bsrf %0\n%O1:%#"
+ [(set_attr "type" "sfunc")
+ (set_attr "needs_delay_slot" "yes")])
+
+ (define_insn "block_lump_real"
+ [(parallel [(set (mem:BLK (reg:SI R4_REG))
+ (mem:BLK (reg:SI R5_REG)))
+- (use (match_operand:SI 0 "arith_reg_operand" "r"))
++ (use (match_operand:SI 0 "arith_reg_operand" "r,r"))
++ (use (match_operand 1 "" "Z,Ccl"))
+ (use (reg:SI R6_REG))
+ (clobber (reg:SI PR_REG))
+ (clobber (reg:SI T_REG))
+@@ -12708,27 +13008,33 @@ (define_insn "block_lump_real"
+ (clobber (reg:SI R6_REG))
+ (clobber (reg:SI R0_REG))])]
+ "TARGET_SH1 && ! TARGET_HARD_SH4"
+- "jsr @%0%#"
++ "@
++ jsr @%0%#
++ bsrf %0\n%O1:%#"
+ [(set_attr "type" "sfunc")
+ (set_attr "needs_delay_slot" "yes")])
+
+ (define_insn "block_move_real_i4"
+ [(parallel [(set (mem:BLK (reg:SI R4_REG))
+ (mem:BLK (reg:SI R5_REG)))
+- (use (match_operand:SI 0 "arith_reg_operand" "r"))
++ (use (match_operand:SI 0 "arith_reg_operand" "r,r"))
++ (use (match_operand 1 "" "Z,Ccl"))
+ (clobber (reg:SI PR_REG))
+ (clobber (reg:SI R0_REG))
+ (clobber (reg:SI R1_REG))
+ (clobber (reg:SI R2_REG))])]
+ "TARGET_HARD_SH4"
+- "jsr @%0%#"
++ "@
++ jsr @%0%#
++ bsrf %0\n%O1:%#"
+ [(set_attr "type" "sfunc")
+ (set_attr "needs_delay_slot" "yes")])
+
+ (define_insn "block_lump_real_i4"
+ [(parallel [(set (mem:BLK (reg:SI R4_REG))
+ (mem:BLK (reg:SI R5_REG)))
+- (use (match_operand:SI 0 "arith_reg_operand" "r"))
++ (use (match_operand:SI 0 "arith_reg_operand" "r,r"))
++ (use (match_operand 1 "" "Z,Ccl"))
+ (use (reg:SI R6_REG))
+ (clobber (reg:SI PR_REG))
+ (clobber (reg:SI T_REG))
+@@ -12740,7 +13046,9 @@ (define_insn "block_lump_real_i4"
+ (clobber (reg:SI R2_REG))
+ (clobber (reg:SI R3_REG))])]
+ "TARGET_HARD_SH4"
+- "jsr @%0%#"
++ "@
++ jsr @%0%#
++ bsrf %0\n%O1:%#"
+ [(set_attr "type" "sfunc")
+ (set_attr "needs_delay_slot" "yes")])
+
+diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt
+index 8875b5d..c2e8aca 100644
+--- a/gcc/config/sh/sh.opt
++++ b/gcc/config/sh/sh.opt
+@@ -264,6 +264,10 @@ mdivsi3_libfunc=
+ Target RejectNegative Joined Var(sh_divsi3_libfunc) Init("")
+ Specify name for 32 bit signed division function
+
++mfdpic
++Target Report Var(TARGET_FDPIC) Init(0)
++Generate ELF FDPIC code
++
+ mfmovd
+ Target RejectNegative Mask(FMOVD)
+ Enable the use of 64-bit floating point registers in fmov instructions. See -mdalign if 64-bit alignment is required.
+diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
+index 1fd773e..fe57b97 100644
+--- a/gcc/doc/install.texi
++++ b/gcc/doc/install.texi
+@@ -1810,6 +1810,9 @@ When neither of these configure options are used, the default will be
+ 128-bit @code{long double} when built against GNU C Library 2.4 and later,
+ 64-bit @code{long double} otherwise.
+
++@item --enable-fdpic
++On SH Linux systems, generate ELF FDPIC code.
++
+ @item --with-gmp=@var{pathname}
+ @itemx --with-gmp-include=@var{pathname}
+ @itemx --with-gmp-lib=@var{pathname}
+diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
+index ebfaaa1..8b26eac 100644
+--- a/gcc/doc/invoke.texi
++++ b/gcc/doc/invoke.texi
+@@ -21178,6 +21178,10 @@ in effect.
+ Prefer zero-displacement conditional branches for conditional move instruction
+ patterns. This can result in faster code on the SH4 processor.
+
++@item -mfdpic
++@opindex fdpic
++Generate code using the FDPIC ABI.
++
+ @end table
+
+ @node Solaris 2 Options
+diff --git a/include/longlong.h b/include/longlong.h
+index a0b2ce1..d7ef671 100644
+--- a/include/longlong.h
++++ b/include/longlong.h
+@@ -1102,6 +1102,33 @@ extern UDItype __umulsidi3 (USItype, USItype);
+ /* This is the same algorithm as __udiv_qrnnd_c. */
+ #define UDIV_NEEDS_NORMALIZATION 1
+
++#ifdef __FDPIC__
++/* FDPIC needs a special version of the asm fragment to extract the
++ code address from the function descriptor. __udiv_qrnnd_16 is
++ assumed to be local and not to use the GOT, so loading r12 is
++ not needed. */
++#define udiv_qrnnd(q, r, n1, n0, d) \
++ do { \
++ extern UWtype __udiv_qrnnd_16 (UWtype, UWtype) \
++ __attribute__ ((visibility ("hidden"))); \
++ /* r0: rn r1: qn */ /* r0: n1 r4: n0 r5: d r6: d1 */ /* r2: __m */ \
++ __asm__ ( \
++ "mov%M4 %4,r5\n" \
++" swap.w %3,r4\n" \
++" swap.w r5,r6\n" \
++" mov.l @%5,r2\n" \
++" jsr @r2\n" \
++" shll16 r6\n" \
++" swap.w r4,r4\n" \
++" mov.l @%5,r2\n" \
++" jsr @r2\n" \
++" swap.w r1,%0\n" \
++" or r1,%0" \
++ : "=r" (q), "=&z" (r) \
++ : "1" (n1), "r" (n0), "rm" (d), "r" (&__udiv_qrnnd_16) \
++ : "r1", "r2", "r4", "r5", "r6", "pr", "t"); \
++ } while (0)
++#else
+ #define udiv_qrnnd(q, r, n1, n0, d) \
+ do { \
+ extern UWtype __udiv_qrnnd_16 (UWtype, UWtype) \
+@@ -1121,6 +1148,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
+ : "1" (n1), "r" (n0), "rm" (d), "r" (&__udiv_qrnnd_16) \
+ : "r1", "r2", "r4", "r5", "r6", "pr", "t"); \
+ } while (0)
++#endif /* __FDPIC__ */
+
+ #define UDIV_TIME 80
+
+diff --git a/libitm/config/sh/sjlj.S b/libitm/config/sh/sjlj.S
+index 410cef6..8c83fce 100644
+--- a/libitm/config/sh/sjlj.S
++++ b/libitm/config/sh/sjlj.S
+@@ -58,9 +58,6 @@ _ITM_beginTransaction:
+ jsr @r1
+ mov r15, r5
+ #else
+- mova .Lgot, r0
+- mov.l .Lgot, r12
+- add r0, r12
+ mov.l .Lbegin, r1
+ bsrf r1
+ mov r15, r5
+@@ -79,14 +76,12 @@ _ITM_beginTransaction:
+ nop
+ cfi_endproc
+
+- .align 2
+-.Lgot:
+- .long _GLOBAL_OFFSET_TABLE_
++ .align 2
+ .Lbegin:
+ #if defined HAVE_ATTRIBUTE_VISIBILITY || !defined __PIC__
+ .long GTM_begin_transaction
+ #else
+- .long GTM_begin_transaction@PLT-(.Lbegin0-.)
++ .long GTM_begin_transaction@PCREL-(.Lbegin0-.)
+ #endif
+ .size _ITM_beginTransaction, . - _ITM_beginTransaction
+
--- /dev/null
+--- a/gcc/config/sh/sh.md (revision 233324)
++++ b/gcc/config/sh/sh.md (working copy)
+@@ -10476,7 +10476,7 @@
+ (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
+ (match_operand 2 "" "")))
+ (use (reg:SI FPSCR_MODES_REG))
+- (clobber (match_scratch:SI 3 "=k"))
++ (clobber (reg:SI R1_REG))
+ (return)]
+ "TARGET_SH2 && !TARGET_FDPIC"
+ "#"
+@@ -10491,6 +10495,8 @@
+ rtx lab = PATTERN (gen_call_site ());
+ rtx call_insn;
+
++ operands[3] = gen_rtx_REG (SImode, R1_REG);
++
+ sh_expand_sym_label2reg (operands[3], operands[1], lab, true);
+ call_insn = emit_call_insn (gen_sibcall_valuei_pcrel (operands[0],
+ operands[3],
+@@ -10511,7 +10519,7 @@
+ (match_operand 2)))
+ (use (reg:SI FPSCR_MODES_REG))
+ (use (reg:SI PIC_REG))
+- (clobber (match_scratch:SI 3 "=k"))
++ (clobber (reg:SI R1_REG))
+ (return)]
+ "TARGET_SH2 && TARGET_FDPIC"
+ "#"
+@@ -10520,6 +10528,8 @@
+ {
+ rtx lab = PATTERN (gen_call_site ());
+
++ operands[3] = gen_rtx_REG (SImode, R1_REG);
++
+ sh_expand_sym_label2reg (operands[3], operands[1], lab, true);
+ rtx i = emit_call_insn (gen_sibcall_valuei_pcrel_fdpic (operands[0],
+ operands[3],
+
--- /dev/null
+--- a/libgcc/config/mips/linux-unwind.h 2016-04-07 23:08:58.088577977 +0000
++++ b/libgcc/config/mips/linux-unwind.h 2016-04-07 23:04:34.016523639 +0000
+@@ -27,7 +27,7 @@
+ state data appropriately. See unwind-dw2.c for the structs. */
+
+ #include <signal.h>
+-#include <asm/unistd.h>
++#include <sys/syscall.h>
+
+ /* The third parameter to the signal handler points to something with
+ * this structure defined in asm/ucontext.h, but the name clashes with
--- /dev/null
+diff --git a/fixincludes/mkfixinc.sh b/fixincludes/mkfixinc.sh
+index 6653fed..0d96c8c 100755
+--- a/fixincludes/mkfixinc.sh
++++ b/fixincludes/mkfixinc.sh
+@@ -19,7 +19,8 @@ case $machine in
+ powerpc-*-eabi* | \
+ powerpc-*-rtems* | \
+ powerpcle-*-eabisim* | \
+- powerpcle-*-eabi* )
++ powerpcle-*-eabi* | \
++ *-musl* )
+ # IF there is no include fixing,
+ # THEN create a no-op fixer and exit
+ (echo "#! /bin/sh" ; echo "exit 0" ) > ${target}
+diff --git a/gcc/config.gcc b/gcc/config.gcc
+index 3ede69b..d9eb8cf 100644
+--- a/gcc/config.gcc
++++ b/gcc/config.gcc
+@@ -575,7 +575,7 @@ case ${target} in
+ esac
+
+ # Common C libraries.
+-tm_defines="$tm_defines LIBC_GLIBC=1 LIBC_UCLIBC=2 LIBC_BIONIC=3"
++tm_defines="$tm_defines LIBC_GLIBC=1 LIBC_UCLIBC=2 LIBC_BIONIC=3 LIBC_MUSL=4"
+
+ # 32-bit x86 processors supported by --with-arch=. Each processor
+ # MUST be separated by exactly one space.
+@@ -720,6 +720,9 @@ case ${target} in
+ *-*-*uclibc*)
+ tm_defines="$tm_defines DEFAULT_LIBC=LIBC_UCLIBC"
+ ;;
++ *-*-*musl*)
++ tm_defines="$tm_defines DEFAULT_LIBC=LIBC_MUSL"
++ ;;
+ *)
+ tm_defines="$tm_defines DEFAULT_LIBC=LIBC_GLIBC"
+ ;;
+diff --git a/gcc/config/aarch64/aarch64-linux.h b/gcc/config/aarch64/aarch64-linux.h
+index ba7fc3b..1600a32 100644
+--- a/gcc/config/aarch64/aarch64-linux.h
++++ b/gcc/config/aarch64/aarch64-linux.h
+@@ -23,6 +23,9 @@
+
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"
+
++#undef MUSL_DYNAMIC_LINKER
++#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-aarch64%{mbig-endian:_be}%{mabi=ilp32:_ilp32}.so.1"
++
+ #undef ASAN_CC1_SPEC
+ #define ASAN_CC1_SPEC "%{%:sanitize(address):-funwind-tables}"
+
+diff --git a/gcc/config/alpha/linux.h b/gcc/config/alpha/linux.h
+index c567f43..475ea06 100644
+--- a/gcc/config/alpha/linux.h
++++ b/gcc/config/alpha/linux.h
+@@ -61,10 +61,14 @@ along with GCC; see the file COPYING3. If not see
+ #define OPTION_GLIBC (DEFAULT_LIBC == LIBC_GLIBC)
+ #define OPTION_UCLIBC (DEFAULT_LIBC == LIBC_UCLIBC)
+ #define OPTION_BIONIC (DEFAULT_LIBC == LIBC_BIONIC)
++#undef OPTION_MUSL
++#define OPTION_MUSL (DEFAULT_LIBC == LIBC_MUSL)
+ #else
+ #define OPTION_GLIBC (linux_libc == LIBC_GLIBC)
+ #define OPTION_UCLIBC (linux_libc == LIBC_UCLIBC)
+ #define OPTION_BIONIC (linux_libc == LIBC_BIONIC)
++#undef OPTION_MUSL
++#define OPTION_MUSL (linux_libc == LIBC_MUSL)
+ #endif
+
+ /* Determine what functions are present at the runtime;
+diff --git a/gcc/config/arm/linux-eabi.h b/gcc/config/arm/linux-eabi.h
+index e9d65dc..f12e6bd 100644
+--- a/gcc/config/arm/linux-eabi.h
++++ b/gcc/config/arm/linux-eabi.h
+@@ -77,6 +77,23 @@
+ %{mfloat-abi=soft*:" GLIBC_DYNAMIC_LINKER_SOFT_FLOAT "} \
+ %{!mfloat-abi=*:" GLIBC_DYNAMIC_LINKER_DEFAULT "}"
+
++/* For ARM musl currently supports four dynamic linkers:
++ - ld-musl-arm.so.1 - for the EABI-derived soft-float ABI
++ - ld-musl-armhf.so.1 - for the EABI-derived hard-float ABI
++ - ld-musl-armeb.so.1 - for the EABI-derived soft-float ABI, EB
++ - ld-musl-armebhf.so.1 - for the EABI-derived hard-float ABI, EB
++ musl does not support the legacy OABI mode.
++ All the dynamic linkers live in /lib.
++ We default to soft-float, EL. */
++#undef MUSL_DYNAMIC_LINKER
++#if TARGET_BIG_ENDIAN_DEFAULT
++#define MUSL_DYNAMIC_LINKER_E "%{mlittle-endian:;:eb}"
++#else
++#define MUSL_DYNAMIC_LINKER_E "%{mbig-endian:eb}"
++#endif
++#define MUSL_DYNAMIC_LINKER \
++ "/lib/ld-musl-arm" MUSL_DYNAMIC_LINKER_E "%{mfloat-abi=hard:hf}.so.1"
++
+ /* At this point, bpabi.h will have clobbered LINK_SPEC. We want to
+ use the GNU/Linux version, not the generic BPABI version. */
+ #undef LINK_SPEC
+diff --git a/gcc/config/glibc-stdint.h b/gcc/config/glibc-stdint.h
+index 3fc67dc..98f4f04 100644
+--- a/gcc/config/glibc-stdint.h
++++ b/gcc/config/glibc-stdint.h
+@@ -22,6 +22,12 @@ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
++/* Systems using musl libc should use this header and make sure
++ OPTION_MUSL is defined correctly before using the TYPE macros. */
++#ifndef OPTION_MUSL
++#define OPTION_MUSL 0
++#endif
++
+ #define SIG_ATOMIC_TYPE "int"
+
+ #define INT8_TYPE "signed char"
+@@ -43,12 +49,12 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ #define UINT_LEAST64_TYPE (LONG_TYPE_SIZE == 64 ? "long unsigned int" : "long long unsigned int")
+
+ #define INT_FAST8_TYPE "signed char"
+-#define INT_FAST16_TYPE (LONG_TYPE_SIZE == 64 ? "long int" : "int")
+-#define INT_FAST32_TYPE (LONG_TYPE_SIZE == 64 ? "long int" : "int")
++#define INT_FAST16_TYPE (LONG_TYPE_SIZE == 64 && !OPTION_MUSL ? "long int" : "int")
++#define INT_FAST32_TYPE (LONG_TYPE_SIZE == 64 && !OPTION_MUSL ? "long int" : "int")
+ #define INT_FAST64_TYPE (LONG_TYPE_SIZE == 64 ? "long int" : "long long int")
+ #define UINT_FAST8_TYPE "unsigned char"
+-#define UINT_FAST16_TYPE (LONG_TYPE_SIZE == 64 ? "long unsigned int" : "unsigned int")
+-#define UINT_FAST32_TYPE (LONG_TYPE_SIZE == 64 ? "long unsigned int" : "unsigned int")
++#define UINT_FAST16_TYPE (LONG_TYPE_SIZE == 64 && !OPTION_MUSL ? "long unsigned int" : "unsigned int")
++#define UINT_FAST32_TYPE (LONG_TYPE_SIZE == 64 && !OPTION_MUSL ? "long unsigned int" : "unsigned int")
+ #define UINT_FAST64_TYPE (LONG_TYPE_SIZE == 64 ? "long unsigned int" : "long long unsigned int")
+
+ #define INTPTR_TYPE (LONG_TYPE_SIZE == 64 ? "long int" : "int")
+diff --git a/gcc/config/i386/linux.h b/gcc/config/i386/linux.h
+index a100963..385aefd 100644
+--- a/gcc/config/i386/linux.h
++++ b/gcc/config/i386/linux.h
+@@ -21,3 +21,6 @@ along with GCC; see the file COPYING3. If not see
+
+ #define GNU_USER_LINK_EMULATION "elf_i386"
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
++
++#undef MUSL_DYNAMIC_LINKER
++#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-i386.so.1"
+diff --git a/gcc/config/i386/linux64.h b/gcc/config/i386/linux64.h
+index a27d3be..e300480 100644
+--- a/gcc/config/i386/linux64.h
++++ b/gcc/config/i386/linux64.h
+@@ -30,3 +30,10 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ #define GLIBC_DYNAMIC_LINKER32 "/lib/ld-linux.so.2"
+ #define GLIBC_DYNAMIC_LINKER64 "/lib64/ld-linux-x86-64.so.2"
+ #define GLIBC_DYNAMIC_LINKERX32 "/libx32/ld-linux-x32.so.2"
++
++#undef MUSL_DYNAMIC_LINKER32
++#define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-i386.so.1"
++#undef MUSL_DYNAMIC_LINKER64
++#define MUSL_DYNAMIC_LINKER64 "/lib/ld-musl-x86_64.so.1"
++#undef MUSL_DYNAMIC_LINKERX32
++#define MUSL_DYNAMIC_LINKERX32 "/lib/ld-musl-x32.so.1"
+diff --git a/gcc/config/linux.h b/gcc/config/linux.h
+index 857389a..7bc87ab 100644
+--- a/gcc/config/linux.h
++++ b/gcc/config/linux.h
+@@ -32,10 +32,14 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ #define OPTION_GLIBC (DEFAULT_LIBC == LIBC_GLIBC)
+ #define OPTION_UCLIBC (DEFAULT_LIBC == LIBC_UCLIBC)
+ #define OPTION_BIONIC (DEFAULT_LIBC == LIBC_BIONIC)
++#undef OPTION_MUSL
++#define OPTION_MUSL (DEFAULT_LIBC == LIBC_MUSL)
+ #else
+ #define OPTION_GLIBC (linux_libc == LIBC_GLIBC)
+ #define OPTION_UCLIBC (linux_libc == LIBC_UCLIBC)
+ #define OPTION_BIONIC (linux_libc == LIBC_BIONIC)
++#undef OPTION_MUSL
++#define OPTION_MUSL (linux_libc == LIBC_MUSL)
+ #endif
+
+ #define GNU_USER_TARGET_OS_CPP_BUILTINS() \
+@@ -50,21 +54,25 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ } while (0)
+
+ /* Determine which dynamic linker to use depending on whether GLIBC or
+- uClibc or Bionic is the default C library and whether
+- -muclibc or -mglibc or -mbionic has been passed to change the default. */
++ uClibc or Bionic or musl is the default C library and whether
++ -muclibc or -mglibc or -mbionic or -mmusl has been passed to change
++ the default. */
+
+-#define CHOOSE_DYNAMIC_LINKER1(LIBC1, LIBC2, LIBC3, LD1, LD2, LD3) \
+- "%{" LIBC2 ":" LD2 ";:%{" LIBC3 ":" LD3 ";:" LD1 "}}"
++#define CHOOSE_DYNAMIC_LINKER1(LIBC1, LIBC2, LIBC3, LIBC4, LD1, LD2, LD3, LD4) \
++ "%{" LIBC2 ":" LD2 ";:%{" LIBC3 ":" LD3 ";:%{" LIBC4 ":" LD4 ";:" LD1 "}}}"
+
+ #if DEFAULT_LIBC == LIBC_GLIBC
+-#define CHOOSE_DYNAMIC_LINKER(G, U, B) \
+- CHOOSE_DYNAMIC_LINKER1 ("mglibc", "muclibc", "mbionic", G, U, B)
++#define CHOOSE_DYNAMIC_LINKER(G, U, B, M) \
++ CHOOSE_DYNAMIC_LINKER1 ("mglibc", "muclibc", "mbionic", "mmusl", G, U, B, M)
+ #elif DEFAULT_LIBC == LIBC_UCLIBC
+-#define CHOOSE_DYNAMIC_LINKER(G, U, B) \
+- CHOOSE_DYNAMIC_LINKER1 ("muclibc", "mglibc", "mbionic", U, G, B)
++#define CHOOSE_DYNAMIC_LINKER(G, U, B, M) \
++ CHOOSE_DYNAMIC_LINKER1 ("muclibc", "mglibc", "mbionic", "mmusl", U, G, B, M)
+ #elif DEFAULT_LIBC == LIBC_BIONIC
+-#define CHOOSE_DYNAMIC_LINKER(G, U, B) \
+- CHOOSE_DYNAMIC_LINKER1 ("mbionic", "mglibc", "muclibc", B, G, U)
++#define CHOOSE_DYNAMIC_LINKER(G, U, B, M) \
++ CHOOSE_DYNAMIC_LINKER1 ("mbionic", "mglibc", "muclibc", "mmusl", B, G, U, M)
++#elif DEFAULT_LIBC == LIBC_MUSL
++#define CHOOSE_DYNAMIC_LINKER(G, U, B, M) \
++ CHOOSE_DYNAMIC_LINKER1 ("mmusl", "mglibc", "muclibc", "mbionic", M, G, U, B)
+ #else
+ #error "Unsupported DEFAULT_LIBC"
+ #endif /* DEFAULT_LIBC */
+@@ -81,24 +89,100 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ #define BIONIC_DYNAMIC_LINKER32 "/system/bin/linker"
+ #define BIONIC_DYNAMIC_LINKER64 "/system/bin/linker64"
+ #define BIONIC_DYNAMIC_LINKERX32 "/system/bin/linkerx32"
++/* Should be redefined for each target that supports musl. */
++#define MUSL_DYNAMIC_LINKER "/dev/null"
++#define MUSL_DYNAMIC_LINKER32 "/dev/null"
++#define MUSL_DYNAMIC_LINKER64 "/dev/null"
++#define MUSL_DYNAMIC_LINKERX32 "/dev/null"
+
+ #define GNU_USER_DYNAMIC_LINKER \
+ CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER, \
+- BIONIC_DYNAMIC_LINKER)
++ BIONIC_DYNAMIC_LINKER, MUSL_DYNAMIC_LINKER)
+ #define GNU_USER_DYNAMIC_LINKER32 \
+ CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER32, UCLIBC_DYNAMIC_LINKER32, \
+- BIONIC_DYNAMIC_LINKER32)
++ BIONIC_DYNAMIC_LINKER32, MUSL_DYNAMIC_LINKER32)
+ #define GNU_USER_DYNAMIC_LINKER64 \
+ CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER64, UCLIBC_DYNAMIC_LINKER64, \
+- BIONIC_DYNAMIC_LINKER64)
++ BIONIC_DYNAMIC_LINKER64, MUSL_DYNAMIC_LINKER64)
+ #define GNU_USER_DYNAMIC_LINKERX32 \
+ CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKERX32, UCLIBC_DYNAMIC_LINKERX32, \
+- BIONIC_DYNAMIC_LINKERX32)
++ BIONIC_DYNAMIC_LINKERX32, MUSL_DYNAMIC_LINKERX32)
+
+ /* Whether we have Bionic libc runtime */
+ #undef TARGET_HAS_BIONIC
+ #define TARGET_HAS_BIONIC (OPTION_BIONIC)
+
++/* musl avoids problematic includes by rearranging the include directories.
++ * Unfortunately, this is mostly duplicated from cppdefault.c */
++#if DEFAULT_LIBC == LIBC_MUSL
++#define INCLUDE_DEFAULTS_MUSL_GPP \
++ { GPLUSPLUS_INCLUDE_DIR, "G++", 1, 1, \
++ GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 0 }, \
++ { GPLUSPLUS_TOOL_INCLUDE_DIR, "G++", 1, 1, \
++ GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 1 }, \
++ { GPLUSPLUS_BACKWARD_INCLUDE_DIR, "G++", 1, 1, \
++ GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 0 },
++
++#ifdef LOCAL_INCLUDE_DIR
++#define INCLUDE_DEFAULTS_MUSL_LOCAL \
++ { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 2 }, \
++ { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 0 },
++#else
++#define INCLUDE_DEFAULTS_MUSL_LOCAL
++#endif
++
++#ifdef PREFIX_INCLUDE_DIR
++#define INCLUDE_DEFAULTS_MUSL_PREFIX \
++ { PREFIX_INCLUDE_DIR, 0, 0, 1, 0, 0},
++#else
++#define INCLUDE_DEFAULTS_MUSL_PREFIX
++#endif
++
++#ifdef CROSS_INCLUDE_DIR
++#define INCLUDE_DEFAULTS_MUSL_CROSS \
++ { CROSS_INCLUDE_DIR, "GCC", 0, 0, 0, 0},
++#else
++#define INCLUDE_DEFAULTS_MUSL_CROSS
++#endif
++
++#ifdef TOOL_INCLUDE_DIR
++#define INCLUDE_DEFAULTS_MUSL_TOOL \
++ { TOOL_INCLUDE_DIR, "BINUTILS", 0, 1, 0, 0},
++#else
++#define INCLUDE_DEFAULTS_MUSL_TOOL
++#endif
++
++#ifdef NATIVE_SYSTEM_HEADER_DIR
++#define INCLUDE_DEFAULTS_MUSL_NATIVE \
++ { NATIVE_SYSTEM_HEADER_DIR, 0, 0, 0, 1, 2 }, \
++ { NATIVE_SYSTEM_HEADER_DIR, 0, 0, 0, 1, 0 },
++#else
++#define INCLUDE_DEFAULTS_MUSL_NATIVE
++#endif
++
++#if defined (CROSS_DIRECTORY_STRUCTURE) && !defined (TARGET_SYSTEM_ROOT)
++# undef INCLUDE_DEFAULTS_MUSL_LOCAL
++# define INCLUDE_DEFAULTS_MUSL_LOCAL
++# undef INCLUDE_DEFAULTS_MUSL_NATIVE
++# define INCLUDE_DEFAULTS_MUSL_NATIVE
++#else
++# undef INCLUDE_DEFAULTS_MUSL_CROSS
++# define INCLUDE_DEFAULTS_MUSL_CROSS
++#endif
++
++#undef INCLUDE_DEFAULTS
++#define INCLUDE_DEFAULTS \
++ { \
++ INCLUDE_DEFAULTS_MUSL_GPP \
++ INCLUDE_DEFAULTS_MUSL_PREFIX \
++ INCLUDE_DEFAULTS_MUSL_CROSS \
++ INCLUDE_DEFAULTS_MUSL_TOOL \
++ INCLUDE_DEFAULTS_MUSL_NATIVE \
++ { GCC_INCLUDE_DIR, "GCC", 0, 1, 0, 0 }, \
++ { 0, 0, 0, 0, 0, 0 } \
++ }
++#endif
++
+ #if (DEFAULT_LIBC == LIBC_UCLIBC) && defined (SINGLE_LIBC) /* uClinux */
+ /* This is a *uclinux* target. We don't define below macros to normal linux
+ versions, because doing so would require *uclinux* targets to include
+diff --git a/gcc/config/linux.opt b/gcc/config/linux.opt
+index c054338..ef055a7 100644
+--- a/gcc/config/linux.opt
++++ b/gcc/config/linux.opt
+@@ -28,5 +28,9 @@ Target Report RejectNegative Var(linux_libc,LIBC_GLIBC) Negative(muclibc)
+ Use GNU C library
+
+ muclibc
+-Target Report RejectNegative Var(linux_libc,LIBC_UCLIBC) Negative(mbionic)
++Target Report RejectNegative Var(linux_libc,LIBC_UCLIBC) Negative(mmusl)
+ Use uClibc C library
++
++mmusl
++Target Report RejectNegative Var(linux_libc,LIBC_MUSL) Negative(mbionic)
++Use musl C library
+diff --git a/gcc/config/microblaze/linux.h b/gcc/config/microblaze/linux.h
+index 655a70f..a8a3f3e 100644
+--- a/gcc/config/microblaze/linux.h
++++ b/gcc/config/microblaze/linux.h
+@@ -28,10 +28,20 @@
+ #undef TLS_NEEDS_GOT
+ #define TLS_NEEDS_GOT 1
+
+-#define DYNAMIC_LINKER "/lib/ld.so.1"
++#define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
++
++#if TARGET_BIG_ENDIAN_DEFAULT == 0 /* LE */
++#define MUSL_DYNAMIC_LINKER_E "%{mbig-endian:;:el}"
++#else
++#define MUSL_DYNAMIC_LINKER_E "%{mlittle-endian:el}"
++#endif
++
++#undef MUSL_DYNAMIC_LINKER
++#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-microblaze" MUSL_DYNAMIC_LINKER_E ".so.1"
++
+ #undef SUBTARGET_EXTRA_SPECS
+ #define SUBTARGET_EXTRA_SPECS \
+- { "dynamic_linker", DYNAMIC_LINKER }
++ { "dynamic_linker", GNU_USER_DYNAMIC_LINKER }
+
+ #undef LINK_SPEC
+ #define LINK_SPEC "%{shared:-shared} \
+diff --git a/gcc/config/mips/linux.h b/gcc/config/mips/linux.h
+index 91df261..fb358e2 100644
+--- a/gcc/config/mips/linux.h
++++ b/gcc/config/mips/linux.h
+@@ -37,7 +37,13 @@ along with GCC; see the file COPYING3. If not see
+ #define UCLIBC_DYNAMIC_LINKERN32 \
+ "%{mnan=2008:/lib32/ld-uClibc-mipsn8.so.0;:/lib32/ld-uClibc.so.0}"
+
++#undef MUSL_DYNAMIC_LINKER32
++#define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-mips%{EL:el}%{msoft-float:-sf}.so.1"
++#undef MUSL_DYNAMIC_LINKER64
++#define MUSL_DYNAMIC_LINKER64 "/lib/ld-musl-mips64%{EL:el}%{msoft-float:-sf}.so.1"
++#define MUSL_DYNAMIC_LINKERN32 "/lib/ld-musl-mipsn32%{EL:el}%{msoft-float:-sf}.so.1"
++
+ #define BIONIC_DYNAMIC_LINKERN32 "/system/bin/linker32"
+ #define GNU_USER_DYNAMIC_LINKERN32 \
+ CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKERN32, UCLIBC_DYNAMIC_LINKERN32, \
+- BIONIC_DYNAMIC_LINKERN32)
++ BIONIC_DYNAMIC_LINKERN32, MUSL_DYNAMIC_LINKERN32)
+diff --git a/gcc/config/rs6000/linux.h b/gcc/config/rs6000/linux.h
+index fe0ebd6..a68ff69 100644
+--- a/gcc/config/rs6000/linux.h
++++ b/gcc/config/rs6000/linux.h
+@@ -30,10 +30,14 @@
+ #define OPTION_GLIBC (DEFAULT_LIBC == LIBC_GLIBC)
+ #define OPTION_UCLIBC (DEFAULT_LIBC == LIBC_UCLIBC)
+ #define OPTION_BIONIC (DEFAULT_LIBC == LIBC_BIONIC)
++#undef OPTION_MUSL
++#define OPTION_MUSL (DEFAULT_LIBC == LIBC_MUSL)
+ #else
+ #define OPTION_GLIBC (linux_libc == LIBC_GLIBC)
+ #define OPTION_UCLIBC (linux_libc == LIBC_UCLIBC)
+ #define OPTION_BIONIC (linux_libc == LIBC_BIONIC)
++#undef OPTION_MUSL
++#define OPTION_MUSL (linux_libc == LIBC_MUSL)
+ #endif
+
+ /* Determine what functions are present at the runtime;
+diff --git a/gcc/config/rs6000/linux64.h b/gcc/config/rs6000/linux64.h
+index 0879e7e..6a7d435 100644
+--- a/gcc/config/rs6000/linux64.h
++++ b/gcc/config/rs6000/linux64.h
+@@ -299,10 +299,14 @@ extern int dot_symbols;
+ #define OPTION_GLIBC (DEFAULT_LIBC == LIBC_GLIBC)
+ #define OPTION_UCLIBC (DEFAULT_LIBC == LIBC_UCLIBC)
+ #define OPTION_BIONIC (DEFAULT_LIBC == LIBC_BIONIC)
++#undef OPTION_MUSL
++#define OPTION_MUSL (DEFAULT_LIBC == LIBC_MUSL)
+ #else
+ #define OPTION_GLIBC (linux_libc == LIBC_GLIBC)
+ #define OPTION_UCLIBC (linux_libc == LIBC_UCLIBC)
+ #define OPTION_BIONIC (linux_libc == LIBC_BIONIC)
++#undef OPTION_MUSL
++#define OPTION_MUSL (linux_libc == LIBC_MUSL)
+ #endif
+
+ /* Determine what functions are present at the runtime;
+@@ -365,17 +369,23 @@ extern int dot_symbols;
+ #endif
+ #define UCLIBC_DYNAMIC_LINKER32 "/lib/ld-uClibc.so.0"
+ #define UCLIBC_DYNAMIC_LINKER64 "/lib/ld64-uClibc.so.0"
++#define MUSL_DYNAMIC_LINKER32 \
++ "/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1"
++#define MUSL_DYNAMIC_LINKER64 \
++ "/lib/ld-musl-powerpc64" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1"
+ #if DEFAULT_LIBC == LIBC_UCLIBC
+-#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
++#define CHOOSE_DYNAMIC_LINKER(G, U, M) "%{mglibc:" G ";:%{mmusl:" M ";:" U "}}"
+ #elif DEFAULT_LIBC == LIBC_GLIBC
+-#define CHOOSE_DYNAMIC_LINKER(G, U) "%{muclibc:" U ";:" G "}"
++#define CHOOSE_DYNAMIC_LINKER(G, U, M) "%{muclibc:" U ";:%{mmusl:" M ";:" G "}}"
++#elif DEFAULT_LIBC == LIBC_MUSL
++#define CHOOSE_DYNAMIC_LINKER(G, U, M) "%{mglibc:" G ";:%{muclibc:" U ";:" M "}}"
+ #else
+ #error "Unsupported DEFAULT_LIBC"
+ #endif
+ #define GNU_USER_DYNAMIC_LINKER32 \
+- CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER32, UCLIBC_DYNAMIC_LINKER32)
++ CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER32, UCLIBC_DYNAMIC_LINKER32, MUSL_DYNAMIC_LINKER32)
+ #define GNU_USER_DYNAMIC_LINKER64 \
+- CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER64, UCLIBC_DYNAMIC_LINKER64)
++ CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER64, UCLIBC_DYNAMIC_LINKER64, MUSL_DYNAMIC_LINKER64)
+
+ #undef DEFAULT_ASM_ENDIAN
+ #if (TARGET_DEFAULT & MASK_LITTLE_ENDIAN)
+diff --git a/gcc/config/rs6000/secureplt.h b/gcc/config/rs6000/secureplt.h
+index b463463..77edf2a 100644
+--- a/gcc/config/rs6000/secureplt.h
++++ b/gcc/config/rs6000/secureplt.h
+@@ -18,3 +18,4 @@ along with GCC; see the file COPYING3. If not see
+ <http://www.gnu.org/licenses/>. */
+
+ #define CC1_SECURE_PLT_DEFAULT_SPEC "-msecure-plt"
++#define LINK_SECURE_PLT_DEFAULT_SPEC "--secure-plt"
+diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h
+index 9917c2f..68365de 100644
+--- a/gcc/config/rs6000/sysv4.h
++++ b/gcc/config/rs6000/sysv4.h
+@@ -537,6 +537,9 @@ ENDIAN_SELECT(" -mbig", " -mlittle", DEFAULT_ASM_ENDIAN)
+ #ifndef CC1_SECURE_PLT_DEFAULT_SPEC
+ #define CC1_SECURE_PLT_DEFAULT_SPEC ""
+ #endif
++#ifndef LINK_SECURE_PLT_DEFAULT_SPEC
++#define LINK_SECURE_PLT_DEFAULT_SPEC ""
++#endif
+
+ /* Pass -G xxx to the compiler. */
+ #undef CC1_SPEC
+@@ -574,7 +577,8 @@
+ %{R*} \
+ %(link_shlib) \
+ %{!T*: %(link_start) } \
+-%(link_os)"
++%(link_os) \
++%{!mbss-plt: %{!msecure-plt: %(link_secure_plt_default)}}"
+
+ /* Shared libraries are not default. */
+ #define LINK_SHLIB_SPEC "\
+@@ -762,17 +766,23 @@ ENDIAN_SELECT(" -mbig", " -mlittle", DEFAULT_ASM_ENDIAN)
+
+ #define LINK_START_LINUX_SPEC ""
+
++#define MUSL_DYNAMIC_LINKER_E ENDIAN_SELECT("","le","")
++
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1"
+ #define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
++#define MUSL_DYNAMIC_LINKER \
++ "/lib/ld-musl-powerpc" MUSL_DYNAMIC_LINKER_E "%{msoft-float:-sf}.so.1"
+ #if DEFAULT_LIBC == LIBC_UCLIBC
+-#define CHOOSE_DYNAMIC_LINKER(G, U) "%{mglibc:" G ";:" U "}"
++#define CHOOSE_DYNAMIC_LINKER(G, U, M) "%{mglibc:" G ";:%{mmusl:" M ";:" U "}}"
++#elif DEFAULT_LIBC == LIBC_MUSL
++#define CHOOSE_DYNAMIC_LINKER(G, U, M) "%{mglibc:" G ";:%{muclibc:" U ";:" M "}}"
+ #elif !defined (DEFAULT_LIBC) || DEFAULT_LIBC == LIBC_GLIBC
+-#define CHOOSE_DYNAMIC_LINKER(G, U) "%{muclibc:" U ";:" G "}"
++#define CHOOSE_DYNAMIC_LINKER(G, U, M) "%{muclibc:" U ";:%{mmusl:" M ";:" G "}}"
+ #else
+ #error "Unsupported DEFAULT_LIBC"
+ #endif
+ #define GNU_USER_DYNAMIC_LINKER \
+- CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER)
++ CHOOSE_DYNAMIC_LINKER (GLIBC_DYNAMIC_LINKER, UCLIBC_DYNAMIC_LINKER, MUSL_DYNAMIC_LINKER)
+
+ #define LINK_OS_LINUX_SPEC "-m elf32ppclinux %{!shared: %{!static: \
+ %{rdynamic:-export-dynamic} \
+@@ -895,6 +905,7 @@ ncrtn.o%s"
+ { "link_os_openbsd", LINK_OS_OPENBSD_SPEC }, \
+ { "link_os_default", LINK_OS_DEFAULT_SPEC }, \
+ { "cc1_secure_plt_default", CC1_SECURE_PLT_DEFAULT_SPEC }, \
++ { "link_secure_plt_default", LINK_SECURE_PLT_DEFAULT_SPEC }, \
+ { "cpp_os_ads", CPP_OS_ADS_SPEC }, \
+ { "cpp_os_yellowknife", CPP_OS_YELLOWKNIFE_SPEC }, \
+ { "cpp_os_mvme", CPP_OS_MVME_SPEC }, \
+@@ -949,3 +960,72 @@ ncrtn.o%s"
+ /* This target uses the sysv4.opt file. */
+ #define TARGET_USES_SYSV4_OPT 1
+
++/* Include order changes for musl, same as in generic linux.h. */
++#if DEFAULT_LIBC == LIBC_MUSL
++#define INCLUDE_DEFAULTS_MUSL_GPP \
++ { GPLUSPLUS_INCLUDE_DIR, "G++", 1, 1, \
++ GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 0 }, \
++ { GPLUSPLUS_TOOL_INCLUDE_DIR, "G++", 1, 1, \
++ GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 1 }, \
++ { GPLUSPLUS_BACKWARD_INCLUDE_DIR, "G++", 1, 1, \
++ GPLUSPLUS_INCLUDE_DIR_ADD_SYSROOT, 0 },
++
++#ifdef LOCAL_INCLUDE_DIR
++#define INCLUDE_DEFAULTS_MUSL_LOCAL \
++ { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 2 }, \
++ { LOCAL_INCLUDE_DIR, 0, 0, 1, 1, 0 },
++#else
++#define INCLUDE_DEFAULTS_MUSL_LOCAL
++#endif
++
++#ifdef PREFIX_INCLUDE_DIR
++#define INCLUDE_DEFAULTS_MUSL_PREFIX \
++ { PREFIX_INCLUDE_DIR, 0, 0, 1, 0, 0},
++#else
++#define INCLUDE_DEFAULTS_MUSL_PREFIX
++#endif
++
++#ifdef CROSS_INCLUDE_DIR
++#define INCLUDE_DEFAULTS_MUSL_CROSS \
++ { CROSS_INCLUDE_DIR, "GCC", 0, 0, 0, 0},
++#else
++#define INCLUDE_DEFAULTS_MUSL_CROSS
++#endif
++
++#ifdef TOOL_INCLUDE_DIR
++#define INCLUDE_DEFAULTS_MUSL_TOOL \
++ { TOOL_INCLUDE_DIR, "BINUTILS", 0, 1, 0, 0},
++#else
++#define INCLUDE_DEFAULTS_MUSL_TOOL
++#endif
++
++#ifdef NATIVE_SYSTEM_HEADER_DIR
++#define INCLUDE_DEFAULTS_MUSL_NATIVE \
++ { NATIVE_SYSTEM_HEADER_DIR, 0, 0, 0, 1, 2 }, \
++ { NATIVE_SYSTEM_HEADER_DIR, 0, 0, 0, 1, 0 },
++#else
++#define INCLUDE_DEFAULTS_MUSL_NATIVE
++#endif
++
++#if defined (CROSS_DIRECTORY_STRUCTURE) && !defined (TARGET_SYSTEM_ROOT)
++# undef INCLUDE_DEFAULTS_MUSL_LOCAL
++# define INCLUDE_DEFAULTS_MUSL_LOCAL
++# undef INCLUDE_DEFAULTS_MUSL_NATIVE
++# define INCLUDE_DEFAULTS_MUSL_NATIVE
++#else
++# undef INCLUDE_DEFAULTS_MUSL_CROSS
++# define INCLUDE_DEFAULTS_MUSL_CROSS
++#endif
++
++#undef INCLUDE_DEFAULTS
++#define INCLUDE_DEFAULTS \
++ { \
++ INCLUDE_DEFAULTS_MUSL_GPP \
++ INCLUDE_DEFAULTS_MUSL_PREFIX \
++ INCLUDE_DEFAULTS_MUSL_CROSS \
++ INCLUDE_DEFAULTS_MUSL_TOOL \
++ INCLUDE_DEFAULTS_MUSL_NATIVE \
++ { GCC_INCLUDE_DIR, "GCC", 0, 1, 0, 0 }, \
++ { 0, 0, 0, 0, 0, 0 } \
++ }
++#endif
+diff --git a/gcc/config/rs6000/sysv4le.h b/gcc/config/rs6000/sysv4le.h
+index 7b1d6a1..064323c 100644
+--- a/gcc/config/rs6000/sysv4le.h
++++ b/gcc/config/rs6000/sysv4le.h
+@@ -35,3 +35,5 @@
+ /* Little-endian PowerPC64 Linux uses the ELF v2 ABI by default. */
+ #define LINUX64_DEFAULT_ABI_ELFv2
+
++#undef MUSL_DYNAMIC_LINKER_E
++#define MUSL_DYNAMIC_LINKER_E ENDIAN_SELECT("","le","le")
+diff --git a/gcc/config/sh/linux.h b/gcc/config/sh/linux.h
+index 0f5d614..4c167c6 100644
+--- a/gcc/config/sh/linux.h
++++ b/gcc/config/sh/linux.h
+@@ -43,6 +43,29 @@ along with GCC; see the file COPYING3. If not see
+
+ #define TARGET_ASM_FILE_END file_end_indicate_exec_stack
+
++#if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
++#define MUSL_DYNAMIC_LINKER_E "%{mb:eb}"
++#else
++#define MUSL_DYNAMIC_LINKER_E "%{!ml:eb}"
++#endif
++
++#if TARGET_CPU_DEFAULT & ( MASK_HARD_SH2A_DOUBLE | MASK_SH4 )
++/* "-nofpu" if any nofpu option is specified */
++#define MUSL_DYNAMIC_LINKER_FP \
++ "%{m1|m2|m2a-nofpu|m3|m4-nofpu|m4-100-nofpu|m4-200-nofpu|m4-300-nofpu|" \
++ "m4-340|m4-400|m4-500|m4al|m5-32media-nofpu|m5-64media-nofpu|" \
++ "m5-compact-nofpu:-nofpu}"
++#else
++/* "-nofpu" if none of the hard fpu options are specified */
++#define MUSL_DYNAMIC_LINKER_FP \
++ "%{m2a|m4|m4-100|m4-200|m4-300|m4a|m5-32media|m5-64media|m5-compact:;:-nofpu}"
++#endif
++
++#undef MUSL_DYNAMIC_LINKER
++#define MUSL_DYNAMIC_LINKER \
++ "/lib/ld-musl-sh" MUSL_DYNAMIC_LINKER_E MUSL_DYNAMIC_LINKER_FP \
++ "%{mfdpic:-fdpic}.so.1"
++
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
+
+ #undef SUBTARGET_LINK_EMUL_SUFFIX
+diff --git a/gcc/configure b/gcc/configure
+index 0037240..66aab9f 100755
+--- a/gcc/configure
++++ b/gcc/configure
+@@ -27742,6 +27742,9 @@ if test "${gcc_cv_libc_provides_ssp+set}" = set; then :
+ else
+ gcc_cv_libc_provides_ssp=no
+ case "$target" in
++ *-*-musl*)
++ # All versions of musl provide stack protector
++ gcc_cv_libc_provides_ssp=yes;;
+ *-*-linux* | *-*-kfreebsd*-gnu | *-*-knetbsd*-gnu)
+ # glibc 2.4 and later provides __stack_chk_fail and
+ # either __stack_chk_guard, or TLS access to stack guard canary.
+@@ -27774,6 +27777,7 @@ fi
+ # <http://gcc.gnu.org/ml/gcc/2008-10/msg00130.html>) and for now
+ # simply assert that glibc does provide this, which is true for all
+ # realistically usable GNU/Hurd configurations.
++ # All supported versions of musl provide it as well
+ gcc_cv_libc_provides_ssp=yes;;
+ *-*-darwin* | *-*-freebsd*)
+ ac_fn_c_check_func "$LINENO" "__stack_chk_fail" "ac_cv_func___stack_chk_fail"
+@@ -27870,6 +27874,9 @@ case "$target" in
+ gcc_cv_target_dl_iterate_phdr=no
+ fi
+ ;;
++ *-linux-musl*)
++ gcc_cv_target_dl_iterate_phdr=yes
++ ;;
+ esac
+
+ if test x$gcc_cv_target_dl_iterate_phdr = xyes; then
+diff --git a/gcc/configure.ac b/gcc/configure.ac
+index 6f38ba1..b81960c 100644
+--- a/gcc/configure.ac
++++ b/gcc/configure.ac
+@@ -5229,6 +5229,9 @@ AC_CACHE_CHECK(__stack_chk_fail in target C library,
+ gcc_cv_libc_provides_ssp,
+ [gcc_cv_libc_provides_ssp=no
+ case "$target" in
++ *-*-musl*)
++ # All versions of musl provide stack protector
++ gcc_cv_libc_provides_ssp=yes;;
+ *-*-linux* | *-*-kfreebsd*-gnu | *-*-knetbsd*-gnu)
+ # glibc 2.4 and later provides __stack_chk_fail and
+ # either __stack_chk_guard, or TLS access to stack guard canary.
+@@ -5255,6 +5258,7 @@ AC_CACHE_CHECK(__stack_chk_fail in target C library,
+ # <http://gcc.gnu.org/ml/gcc/2008-10/msg00130.html>) and for now
+ # simply assert that glibc does provide this, which is true for all
+ # realistically usable GNU/Hurd configurations.
++ # All supported versions of musl provide it as well
+ gcc_cv_libc_provides_ssp=yes;;
+ *-*-darwin* | *-*-freebsd*)
+ AC_CHECK_FUNC(__stack_chk_fail,[gcc_cv_libc_provides_ssp=yes],
+@@ -5328,6 +5332,9 @@ case "$target" in
+ gcc_cv_target_dl_iterate_phdr=no
+ fi
+ ;;
++ *-linux-musl*)
++ gcc_cv_target_dl_iterate_phdr=yes
++ ;;
+ esac
+ GCC_TARGET_TEMPLATE([TARGET_DL_ITERATE_PHDR])
+ if test x$gcc_cv_target_dl_iterate_phdr = xyes; then
+diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
+index f84a199..ee9765b 100644
+--- a/gcc/doc/invoke.texi
++++ b/gcc/doc/invoke.texi
+@@ -667,7 +667,7 @@ Objective-C and Objective-C++ Dialects}.
+ -mcpu=@var{cpu}}
+
+ @emph{GNU/Linux Options}
+-@gccoptlist{-mglibc -muclibc -mbionic -mandroid @gol
++@gccoptlist{-mglibc -muclibc -mmusl -mbionic -mandroid @gol
+ -tno-android-cc -tno-android-ld}
+
+ @emph{H8/300 Options}
+@@ -15324,13 +15324,19 @@ These @samp{-m} options are defined for GNU/Linux targets:
+ @item -mglibc
+ @opindex mglibc
+ Use the GNU C library. This is the default except
+-on @samp{*-*-linux-*uclibc*} and @samp{*-*-linux-*android*} targets.
++on @samp{*-*-linux-*uclibc*}, @samp{*-*-linux-*musl*} and
++@samp{*-*-linux-*android*} targets.
+
+ @item -muclibc
+ @opindex muclibc
+ Use uClibc C library. This is the default on
+ @samp{*-*-linux-*uclibc*} targets.
+
++@item -mmusl
++@opindex mmusl
++Use the musl C library. This is the default on
++@samp{*-*-linux-*musl*} targets.
++
+ @item -mbionic
+ @opindex mbionic
+ Use Bionic C library. This is the default on
+diff --git a/libcilkrts/runtime/os-unix.c b/libcilkrts/runtime/os-unix.c
+index cb582dd..e43d7d5 100644
+--- a/libcilkrts/runtime/os-unix.c
++++ b/libcilkrts/runtime/os-unix.c
+@@ -51,6 +51,7 @@
+ #if defined __linux__
+ # include <sys/sysinfo.h>
+ # include <sys/syscall.h>
++# include <sched.h>
+ #elif defined __APPLE__
+ # include <sys/sysctl.h>
+ // Uses sysconf(_SC_NPROCESSORS_ONLN) in verbose output
+@@ -400,28 +401,19 @@ COMMON_SYSDEP void __cilkrts_sleep(void)
+
+ COMMON_SYSDEP void __cilkrts_yield(void)
+ {
+-#if __APPLE__ || __FreeBSD__ || __VXWORKS__
+- // On MacOS, call sched_yield to yield quantum. I'm not sure why we
+- // don't do this on Linux also.
+- sched_yield();
+-#elif defined(__DragonFly__)
+- // On DragonFly BSD, call sched_yield to yield quantum.
+- sched_yield();
+-#elif defined(__MIC__)
++#if defined(__MIC__)
+ // On MIC, pthread_yield() really trashes things. Arch's measurements
+ // showed that calling _mm_delay_32() (or doing nothing) was a better
+ // option. Delaying 1024 clock cycles is a reasonable compromise between
+ // giving up the processor and latency starting up when work becomes
+ // available
+ _mm_delay_32(1024);
+-#elif defined(__ANDROID__) || (defined(__sun__) && defined(__svr4__))
+- // On Android and Solaris, call sched_yield to yield quantum. I'm not
+- // sure why we don't do this on Linux also.
+- sched_yield();
+-#else
+- // On Linux, call pthread_yield (which in turn will call sched_yield)
+- // to yield quantum.
++#elif defined(__sun__) && !defined(__svr4__)
++ // On old SunOS call pthread_yield to yield a quantum.
+ pthread_yield();
++#else
++ // On other platforms call sched_yield to yield a quantum.
++ sched_yield();
+ #endif
+ }
+
+diff --git a/libgcc/unwind-dw2-fde-dip.c b/libgcc/unwind-dw2-fde-dip.c
+index e1e566b..137dced 100644
+--- a/libgcc/unwind-dw2-fde-dip.c
++++ b/libgcc/unwind-dw2-fde-dip.c
+@@ -59,6 +59,12 @@
+
+ #if !defined(inhibit_libc) && defined(HAVE_LD_EH_FRAME_HDR) \
+ && defined(TARGET_DL_ITERATE_PHDR) \
++ && defined(__linux__)
++# define USE_PT_GNU_EH_FRAME
++#endif
++
++#if !defined(inhibit_libc) && defined(HAVE_LD_EH_FRAME_HDR) \
++ && defined(TARGET_DL_ITERATE_PHDR) \
+ && (defined(__DragonFly__) || defined(__FreeBSD__))
+ # define ElfW __ElfN
+ # define USE_PT_GNU_EH_FRAME
+diff --git a/libgfortran/acinclude.m4 b/libgfortran/acinclude.m4
+index ba890f9..30b8b1a6 100644
+--- a/libgfortran/acinclude.m4
++++ b/libgfortran/acinclude.m4
+@@ -100,7 +100,7 @@ void foo (void);
+ [Define to 1 if the target supports #pragma weak])
+ fi
+ case "$host" in
+- *-*-darwin* | *-*-hpux* | *-*-cygwin* | *-*-mingw* )
++ *-*-darwin* | *-*-hpux* | *-*-cygwin* | *-*-mingw* | *-*-musl* )
+ AC_DEFINE(GTHREAD_USE_WEAK, 0,
+ [Define to 0 if the target shouldn't use #pragma weak])
+ ;;
+diff --git a/libgfortran/configure b/libgfortran/configure
+index e1592f7..07542e1 100755
+--- a/libgfortran/configure
++++ b/libgfortran/configure
+@@ -26447,7 +26447,7 @@ $as_echo "#define SUPPORTS_WEAK 1" >>confdefs.h
+
+ fi
+ case "$host" in
+- *-*-darwin* | *-*-hpux* | *-*-cygwin* | *-*-mingw* )
++ *-*-darwin* | *-*-hpux* | *-*-cygwin* | *-*-mingw* | *-*-musl* )
+
+ $as_echo "#define GTHREAD_USE_WEAK 0" >>confdefs.h
+
+diff --git a/libitm/config/arm/hwcap.cc b/libitm/config/arm/hwcap.cc
+index a1c2cfd..ea8f023 100644
+--- a/libitm/config/arm/hwcap.cc
++++ b/libitm/config/arm/hwcap.cc
+@@ -40,7 +40,7 @@ int GTM_hwcap HIDDEN = 0
+
+ #ifdef __linux__
+ #include <unistd.h>
+-#include <sys/fcntl.h>
++#include <fcntl.h>
+ #include <elf.h>
+
+ static void __attribute__((constructor))
+diff --git a/libitm/config/linux/x86/tls.h b/libitm/config/linux/x86/tls.h
+index e731ab7..54ad8b6 100644
+--- a/libitm/config/linux/x86/tls.h
++++ b/libitm/config/linux/x86/tls.h
+@@ -25,16 +25,19 @@
+ #ifndef LIBITM_X86_TLS_H
+ #define LIBITM_X86_TLS_H 1
+
+-#if defined(__GLIBC_PREREQ) && __GLIBC_PREREQ(2, 10)
++#if defined(__GLIBC_PREREQ)
++#if __GLIBC_PREREQ(2, 10)
+ /* Use slots in the TCB head rather than __thread lookups.
+ GLIBC has reserved words 10 through 13 for TM. */
+ #define HAVE_ARCH_GTM_THREAD 1
+ #define HAVE_ARCH_GTM_THREAD_DISP 1
+ #endif
++#endif
+
+ #include "config/generic/tls.h"
+
+-#if defined(__GLIBC_PREREQ) && __GLIBC_PREREQ(2, 10)
++#if defined(__GLIBC_PREREQ)
++#if __GLIBC_PREREQ(2, 10)
+ namespace GTM HIDDEN {
+
+ #ifdef __x86_64__
+@@ -101,5 +104,6 @@ static inline void set_abi_disp(struct abi_dispatch *x)
+
+ } // namespace GTM
+ #endif /* >= GLIBC 2.10 */
++#endif
+
+ #endif // LIBITM_X86_TLS_H
+diff --git a/libstdc++-v3/config/os/generic/os_defines.h b/libstdc++-v3/config/os/generic/os_defines.h
+index 45bf52a..103ec0e 100644
+--- a/libstdc++-v3/config/os/generic/os_defines.h
++++ b/libstdc++-v3/config/os/generic/os_defines.h
+@@ -33,4 +33,9 @@
+ // System-specific #define, typedefs, corrections, etc, go here. This
+ // file will come before all others.
+
++// Disable the weak reference logic in gthr.h for os/generic because it
++// is broken on every platform unless there is implementation specific
++// workaround in gthr-posix.h and at link-time for static linking.
++#define _GLIBCXX_GTHREAD_USE_WEAK 0
++
+ #endif
+diff --git a/libstdc++-v3/configure.host b/libstdc++-v3/configure.host
+index 640199c..106134e 100644
+--- a/libstdc++-v3/configure.host
++++ b/libstdc++-v3/configure.host
+@@ -273,6 +273,9 @@ case "${host_os}" in
+ freebsd*)
+ os_include_dir="os/bsd/freebsd"
+ ;;
++ linux-musl*)
++ os_include_dir="os/generic"
++ ;;
+ gnu* | linux* | kfreebsd*-gnu | knetbsd*-gnu)
+ if [ "$uclibc" = "yes" ]; then
+ os_include_dir="os/uclibc"
--- /dev/null
+--- a/gcc/config/sh/sh-protos.h
++++ a/gcc/config/sh/sh-protos.h
+@@ -159,6 +159,7 @@ extern int sh_eval_treg_value (rtx op);
+ extern HOST_WIDE_INT sh_disp_addr_displacement (rtx mem_op);
+ extern int sh_max_mov_insn_displacement (machine_mode mode, bool consider_sh2a);
+ extern bool sh_movsf_ie_ra_split_p (rtx, rtx, rtx);
++extern void sh_expand_sym_label2reg (rtx, rtx, rtx, bool);
+
+ /* Result value of sh_find_set_of_reg. */
+ struct set_of_reg
+--- a/gcc/config/sh/sh.c
++++ a/gcc/config/sh/sh.c
+@@ -1604,6 +1604,10 @@ sh_asm_output_addr_const_extra (FILE *file, rtx x)
+ output_addr_const (file, XVECEXP (x, 0, 0));
+ fputs ("@GOTPLT", file);
+ break;
++ case UNSPEC_PCREL:
++ output_addr_const (file, XVECEXP (x, 0, 0));
++ fputs ("@PCREL", file);
++ break;
+ case UNSPEC_DTPOFF:
+ output_addr_const (file, XVECEXP (x, 0, 0));
+ fputs ("@DTPOFF", file);
+@@ -10441,6 +10445,7 @@ nonpic_symbol_mentioned_p (rtx x)
+ || XINT (x, 1) == UNSPEC_DTPOFF
+ || XINT (x, 1) == UNSPEC_TPOFF
+ || XINT (x, 1) == UNSPEC_PLT
++ || XINT (x, 1) == UNSPEC_PCREL
+ || XINT (x, 1) == UNSPEC_SYMOFF
+ || XINT (x, 1) == UNSPEC_PCREL_SYMOFF))
+ return false;
+@@ -10714,7 +10719,8 @@ sh_delegitimize_address (rtx orig_x)
+ rtx symplt = XEXP (XVECEXP (y, 0, 0), 0);
+
+ if (GET_CODE (symplt) == UNSPEC
+- && XINT (symplt, 1) == UNSPEC_PLT)
++ && (XINT (symplt, 1) == UNSPEC_PLT
++ || XINT (symplt, 1) == UNSPEC_PCREL))
+ return XVECEXP (symplt, 0, 0);
+ }
+ }
+@@ -11702,9 +11708,24 @@ sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
+ || crtl->args.info.stack_regs == 0)
+ && ! sh_cfun_interrupt_handler_p ()
+ && (! flag_pic
+- || (decl && ! TREE_PUBLIC (decl))
++ || (decl && ! (TREE_PUBLIC (decl) || DECL_WEAK (decl)))
+ || (decl && DECL_VISIBILITY (decl) != VISIBILITY_DEFAULT)));
+ }
++
++/* Expand to appropriate sym*_label2reg for SYM and SIBCALL_P. */
++void
++sh_expand_sym_label2reg (rtx reg, rtx sym, rtx lab, bool sibcall_p)
++{
++ const_tree decl = SYMBOL_REF_DECL (sym);
++ bool is_weak = (decl && DECL_P (decl) && DECL_WEAK (decl));
++
++ if (!is_weak && SYMBOL_REF_LOCAL_P (sym))
++ emit_insn (gen_sym_label2reg (reg, sym, lab));
++ else if (sibcall_p)
++ emit_insn (gen_symPCREL_label2reg (reg, sym, lab));
++ else
++ emit_insn (gen_symPLT_label2reg (reg, sym, lab));
++}
+ \f
+ /* Machine specific built-in functions. */
+
+--- a/gcc/config/sh/sh.md
++++ a/gcc/config/sh/sh.md
+@@ -135,6 +135,7 @@
+ UNSPEC_PLT
+ UNSPEC_CALLER
+ UNSPEC_GOTPLT
++ UNSPEC_PCREL
+ UNSPEC_ICACHE
+ UNSPEC_INIT_TRAMP
+ UNSPEC_FCOSA
+@@ -9470,11 +9471,8 @@ label:
+ [(const_int 0)]
+ {
+ rtx lab = PATTERN (gen_call_site ());
+-
+- if (SYMBOL_REF_LOCAL_P (operands[0]))
+- emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
+- else
+- emit_insn (gen_symPLT_label2reg (operands[2], operands[0], lab));
++
++ sh_expand_sym_label2reg (operands[2], operands[0], lab, false);
+ emit_call_insn (gen_calli_pcrel (operands[2], operands[1], copy_rtx (lab)));
+ DONE;
+ }
+@@ -9605,10 +9603,7 @@ label:
+ {
+ rtx lab = PATTERN (gen_call_site ());
+
+- if (SYMBOL_REF_LOCAL_P (operands[1]))
+- emit_insn (gen_sym_label2reg (operands[3], operands[1], lab));
+- else
+- emit_insn (gen_symPLT_label2reg (operands[3], operands[1], lab));
++ sh_expand_sym_label2reg (operands[3], operands[1], lab, false);
+ emit_call_insn (gen_call_valuei_pcrel (operands[0], operands[3],
+ operands[2], copy_rtx (lab)));
+ DONE;
+@@ -10008,7 +10003,7 @@ label:
+ rtx lab = PATTERN (gen_call_site ());
+ rtx call_insn;
+
+- emit_insn (gen_sym_label2reg (operands[2], operands[0], lab));
++ sh_expand_sym_label2reg (operands[2], operands[0], lab, true);
+ call_insn = emit_call_insn (gen_sibcalli_pcrel (operands[2], operands[1],
+ copy_rtx (lab)));
+ SIBLING_CALL_P (call_insn) = 1;
+@@ -10200,7 +10195,7 @@ label:
+ rtx lab = PATTERN (gen_call_site ());
+ rtx call_insn;
+
+- emit_insn (gen_sym_label2reg (operands[3], operands[1], lab));
++ sh_expand_sym_label2reg (operands[3], operands[1], lab, true);
+ call_insn = emit_call_insn (gen_sibcall_valuei_pcrel (operands[0],
+ operands[3],
+ operands[2],
+@@ -10748,6 +10743,16 @@ label:
+ UNSPEC_SYMOFF)))]
+ "TARGET_SH1" "")
+
++(define_expand "symPCREL_label2reg"
++ [(set (match_operand:SI 0 "" "")
++ (const:SI
++ (unspec:SI
++ [(const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PCREL))
++ (const:SI (plus:SI (match_operand:SI 2 "" "")
++ (const_int 2)))] UNSPEC_PCREL_SYMOFF)))]
++ "TARGET_SH1"
++ "")
++
+ (define_expand "symGOT_load"
+ [(set (match_dup 2) (match_operand 1 "" ""))
+ (set (match_dup 3) (plus (match_dup 2) (reg PIC_REG)))
--- /dev/null
+--- gcc-5.2.0.orig/gcc/config.gcc
++++ gcc-5.2.0/gcc/config.gcc
+@@ -4096,7 +4099,7 @@
+ esac
+ ;;
+
+- sh[123456ble]-*-* | sh-*-*)
++ sh[123456ble]*-*-* | sh-*-*)
+ supported_defaults="cpu"
+ case "`echo $with_cpu | tr ABCDEFGHIJKLMNOPQRSTUVWXYZ_ abcdefghijklmnopqrstuvwxyz- | sed s/sh/m/`" in
+ "" | m1 | m2 | m2e | m3 | m3e | m4 | m4-single | m4-single-only | m4-nofpu )
+--- gcc-5.2.0.base/gcc/configure.ac 2015-08-11 16:23:36.000000000 +0000
++++ gcc-5.2.0/gcc/configure.ac 2015-09-13 08:17:31.714972082 +0000
+@@ -3300,7 +3300,7 @@
+ tls_first_minor=14
+ tls_as_opt="-m64 -Aesame --fatal-warnings"
+ ;;
+- sh-*-* | sh[34]-*-*)
++ sh-*-* | sh[123456789lbe]*-*-*)
+ conftest_s='
+ .section ".tdata","awT",@progbits
+ foo: .long 25
+--- gcc-5.2.0.base/gcc/configure 2015-08-11 16:23:35.000000000 +0000
++++ gcc-5.2.0/gcc/configure 2015-09-13 08:17:42.608304751 +0000
+@@ -23754,7 +23754,7 @@
+ tls_first_minor=14
+ tls_as_opt="-m64 -Aesame --fatal-warnings"
+ ;;
+- sh-*-* | sh[34]-*-*)
++ sh-*-* | sh[123456789lbe]*-*-*)
+ conftest_s='
+ .section ".tdata","awT",@progbits
+ foo: .long 25
--- /dev/null
+diff --git a/gcc/config.gcc b/gcc/config.gcc
+index 0f2dc32..a3d0d45 100644
+--- a/gcc/config.gcc
++++ b/gcc/config.gcc
+@@ -467,7 +467,7 @@ s390*-*-*)
+ extra_headers="s390intrin.h htmintrin.h htmxlintrin.h vecintrin.h"
+ ;;
+ # Note the 'l'; we need to be able to match e.g. "shle" or "shl".
+-sh[123456789lbe]*-*-* | sh-*-*)
++sh[123456789lbej]*-*-* | sh-*-*)
+ cpu_type=sh
+ extra_options="${extra_options} fused-madd.opt"
+ extra_objs="${extra_objs} sh_treg_combine.o sh-mem.o sh_optimize_sett_clrt.o"
+@@ -2601,19 +2601,19 @@ s390x-ibm-tpf*)
+ extra_options="${extra_options} s390/tpf.opt"
+ tmake_file="${tmake_file} s390/t-s390"
+ ;;
+-sh-*-elf* | sh[12346l]*-*-elf* | \
+- sh-*-linux* | sh[2346lbe]*-*-linux* | \
++sh-*-elf* | sh[12346lj]*-*-elf* | \
++ sh-*-linux* | sh[2346lbej]*-*-linux* | \
+ sh-*-netbsdelf* | shl*-*-netbsdelf* | sh5-*-netbsd* | sh5l*-*-netbsd* | \
+ sh64-*-netbsd* | sh64l*-*-netbsd*)
+ tmake_file="${tmake_file} sh/t-sh sh/t-elf"
+ if test x${with_endian} = x; then
+ case ${target} in
+- sh[1234]*be-*-* | sh[1234]*eb-*-*) with_endian=big ;;
++ sh[j1234]*be-*-* | sh[j1234]*eb-*-*) with_endian=big ;;
+ shbe-*-* | sheb-*-*) with_endian=big,little ;;
+ sh[1234]l* | sh[34]*-*-linux*) with_endian=little ;;
+ shl* | sh64l* | sh*-*-linux* | \
+ sh5l* | sh-superh-elf) with_endian=little,big ;;
+- sh[1234]*-*-*) with_endian=big ;;
++ sh[j1234]*-*-*) with_endian=big ;;
+ *) with_endian=big,little ;;
+ esac
+ fi
+@@ -2703,6 +2703,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
+ sh2a_nofpu*) sh_cpu_target=sh2a-nofpu ;;
+ sh2a*) sh_cpu_target=sh2a ;;
+ sh2e*) sh_cpu_target=sh2e ;;
++ shj2*) sh_cpu_target=shj2;;
+ sh2*) sh_cpu_target=sh2 ;;
+ *) sh_cpu_target=sh1 ;;
+ esac
+@@ -2727,7 +2728,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
+ sh2a-single-only | sh2a-single | sh2a-nofpu | sh2a | \
+ sh4a-single-only | sh4a-single | sh4a-nofpu | sh4a | sh4al | \
+ sh4-single-only | sh4-single | sh4-nofpu | sh4 | sh4-300 | \
+- sh3e | sh3 | sh2e | sh2 | sh1) ;;
++ sh3e | sh3 | sh2e | sh2 | sh1 | shj2) ;;
+ "") sh_cpu_default=${sh_cpu_target} ;;
+ *) echo "with_cpu=$with_cpu not supported"; exit 1 ;;
+ esac
+@@ -2738,9 +2739,9 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
+ sh[1234]*) sh_multilibs=${sh_cpu_target} ;;
+ sh64* | sh5*) sh_multilibs=m5-32media,m5-32media-nofpu,m5-compact,m5-compact-nofpu,m5-64media,m5-64media-nofpu ;;
+ sh-superh-*) sh_multilibs=m4,m4-single,m4-single-only,m4-nofpu ;;
+- sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4 ;;
++ sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4,mj2 ;;
+ sh*-*-netbsd*) sh_multilibs=m3,m3e,m4 ;;
+- *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single ;;
++ *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single,mj2 ;;
+ esac
+ if test x$with_fp = xno; then
+ sh_multilibs="`echo $sh_multilibs|sed -e s/m4/sh4-nofpu/ -e s/,m4-[^,]*//g -e s/,m[23]e// -e s/m2a,m2a-single/m2a-nofpu/ -e s/m5-..m....,//g`"
+@@ -2758,7 +2759,8 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
+ m2a | m2a-single | m2a-single-only | m2a-nofpu | \
+ m5-64media | m5-64media-nofpu | \
+ m5-32media | m5-32media-nofpu | \
+- m5-compact | m5-compact-nofpu)
++ m5-compact | m5-compact-nofpu | \
++ mj2)
+ # TM_MULTILIB_CONFIG is used by t-sh for the non-endian multilib definition
+ # It is passed to MULTIILIB_OPTIONS verbatim.
+ TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG}/${sh_multilib}"
+@@ -2775,7 +2777,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
+ done
+ TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's:^/::'`
+ if test x${enable_incomplete_targets} = xyes ; then
+- tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SH5_32MEDIA=1 SUPPORT_SH5_32MEDIA_NOFPU=1 SUPPORT_SH5_64MEDIA=1 SUPPORT_SH5_64MEDIA_NOFPU=1"
++ tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SH5_32MEDIA=1 SUPPORT_SH5_32MEDIA_NOFPU=1 SUPPORT_SH5_64MEDIA=1 SUPPORT_SH5_64MEDIA_NOFPU=1 SUPPORT_SHJ2=1"
+ fi
+ tm_file="$tm_file ./sysroot-suffix.h"
+ tmake_file="$tmake_file t-sysroot-suffix"
+@@ -4106,6 +4109,8 @@
+ ;;
+ m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al)
+ ;;
++ mj2)
++ ;;
+ *)
+ echo "Unknown CPU used in --with-cpu=$with_cpu, known values:" 1>&2
+ echo "m1 m2 m2e m3 m3e m4 m4-single m4-single-only m4-nofpu" 1>&2
+@@ -4456,7 +4458,7 @@ case ${target} in
+ tmake_file="rs6000/t-rs6000 ${tmake_file}"
+ ;;
+
+- sh[123456ble]*-*-* | sh-*-*)
++ sh[123456blej]*-*-* | sh-*-*)
+ c_target_objs="${c_target_objs} sh-c.o"
+ cxx_target_objs="${cxx_target_objs} sh-c.o"
+ ;;
+diff --git a/gcc/config/sh/sh-protos.h b/gcc/config/sh/sh-protos.h
+index b08120d..63b77fa 100644
+--- a/gcc/config/sh/sh-protos.h
++++ b/gcc/config/sh/sh-protos.h
+@@ -45,6 +45,7 @@ struct sh_atomic_model
+ hard_llcs,
+ soft_tcb,
+ soft_imask,
++ hard_cas,
+
+ num_models
+ };
+@@ -88,6 +89,9 @@ extern const sh_atomic_model& selected_atomic_model (void);
+ #define TARGET_ATOMIC_SOFT_IMASK \
+ (selected_atomic_model ().type == sh_atomic_model::soft_imask)
+
++#define TARGET_ATOMIC_HARD_CAS \
++ (selected_atomic_model ().type == sh_atomic_model::hard_cas)
++
+ #ifdef RTX_CODE
+ extern rtx sh_fsca_sf2int (void);
+ extern rtx sh_fsca_int2sf (void);
+diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
+index 0b18ce5..bdf96e2 100644
+--- a/gcc/config/sh/sh.c
++++ b/gcc/config/sh/sh.c
+@@ -692,6 +692,7 @@ parse_validate_atomic_model_option (const char* str)
+ model_names[sh_atomic_model::hard_llcs] = "hard-llcs";
+ model_names[sh_atomic_model::soft_tcb] = "soft-tcb";
+ model_names[sh_atomic_model::soft_imask] = "soft-imask";
++ model_names[sh_atomic_model::hard_cas] = "hard-cas";
+
+ const char* model_cdef_names[sh_atomic_model::num_models];
+ model_cdef_names[sh_atomic_model::none] = "NONE";
+@@ -699,6 +700,7 @@ parse_validate_atomic_model_option (const char* str)
+ model_cdef_names[sh_atomic_model::hard_llcs] = "HARD_LLCS";
+ model_cdef_names[sh_atomic_model::soft_tcb] = "SOFT_TCB";
+ model_cdef_names[sh_atomic_model::soft_imask] = "SOFT_IMASK";
++ model_cdef_names[sh_atomic_model::hard_cas] = "HARD_CAS";
+
+ sh_atomic_model ret;
+ ret.type = sh_atomic_model::none;
+@@ -780,6 +782,9 @@ got_mode_name:;
+ if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE)
+ err_ret ("cannot use atomic model %s in user mode", ret.name);
+
++ if (ret.type == sh_atomic_model::hard_cas && !TARGET_SHJ2)
++ err_ret ("atomic model %s is only available J2 targets", ret.name);
++
+ return ret;
+
+ #undef err_ret
+@@ -845,6 +850,8 @@ sh_option_override (void)
+ sh_cpu = PROCESSOR_SH2E;
+ if (TARGET_SH2A)
+ sh_cpu = PROCESSOR_SH2A;
++ if (TARGET_SHJ2)
++ sh_cpu = PROCESSOR_SHJ2;
+ if (TARGET_SH3)
+ sh_cpu = PROCESSOR_SH3;
+ if (TARGET_SH3E)
+diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
+index 7187c23..9d0d1d0 100644
+--- a/gcc/config/sh/sh.h
++++ b/gcc/config/sh/sh.h
+@@ -106,6 +106,7 @@ extern int code_for_indirect_jump_scratch;
+ #define SUPPORT_SH4_SINGLE 1
+ #define SUPPORT_SH2A 1
+ #define SUPPORT_SH2A_SINGLE 1
++#define SUPPORT_SHJ2 1
+ #endif
+
+ #define TARGET_DIVIDE_INV \
+@@ -157,6 +158,7 @@ extern int code_for_indirect_jump_scratch;
+ #define SELECT_SH5_32MEDIA_NOFPU (MASK_SH5 | MASK_SH_E)
+ #define SELECT_SH5_COMPACT (MASK_SH5 | MASK_SH4 | SELECT_SH3E)
+ #define SELECT_SH5_COMPACT_NOFPU (MASK_SH5 | SELECT_SH3)
++#define SELECT_SHJ2 (MASK_SHJ2 | SELECT_SH2)
+
+ #if SUPPORT_SH1
+ #define SUPPORT_SH2 1
+@@ -164,6 +166,7 @@ extern int code_for_indirect_jump_scratch;
+ #if SUPPORT_SH2
+ #define SUPPORT_SH3 1
+ #define SUPPORT_SH2A_NOFPU 1
++#define SUPPORT_SHJ2 1
+ #endif
+ #if SUPPORT_SH3
+ #define SUPPORT_SH4_NOFPU 1
+@@ -211,7 +214,7 @@ extern int code_for_indirect_jump_scratch;
+ #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
+ | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
+ | MASK_HARD_SH4 | MASK_FPU_SINGLE | MASK_SH5 \
+- | MASK_FPU_SINGLE_ONLY)
++ | MASK_FPU_SINGLE_ONLY | MASK_SHJ2)
+
+ /* This defaults us to big-endian. */
+ #ifndef TARGET_ENDIAN_DEFAULT
+@@ -289,8 +292,8 @@ extern int code_for_indirect_jump_scratch;
+ %{m5-compact*:--isa=SHcompact} \
+ %{m5-32media*:--isa=SHmedia --abi=32} \
+ %{m5-64media*:--isa=SHmedia --abi=64} \
+-%{m4al:-dsp} %{mcut2-workaround:-cut2-workaround}"
+-
++%{m4al:-dsp} %{mcut2-workaround:-cut2-workaround} \
++%{mj2:-isa=j2}"
+ #define ASM_SPEC SH_ASM_SPEC
+
+ #ifndef SUBTARGET_ASM_ENDIAN_SPEC
+@@ -1853,7 +1856,7 @@ struct sh_args {
+
+ /* Nonzero if the target supports dynamic shift instructions
+ like shad and shld. */
+-#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A)
++#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A || TARGET_SHJ2)
+
+ /* The cost of using the dynamic shift insns (shad, shld) are the same
+ if they are available. If they are not available a library function will
+@@ -2185,6 +2188,7 @@ enum processor_type {
+ PROCESSOR_SH2,
+ PROCESSOR_SH2E,
+ PROCESSOR_SH2A,
++ PROCESSOR_SHJ2,
+ PROCESSOR_SH3,
+ PROCESSOR_SH3E,
+ PROCESSOR_SH4,
+diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt
+index 1026c73..bac47ed 100644
+--- a/gcc/config/sh/sh.opt
++++ b/gcc/config/sh/sh.opt
+@@ -71,6 +71,10 @@ m2e
+ Target RejectNegative Condition(SUPPORT_SH2E)
+ Generate SH2e code.
+
++mj2
++Target RejectNegative Mask(SHJ2) Condition(SUPPORT_SHJ2)
++Generate J2 code.
++
+ m3
+ Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3)
+ Generate SH3 code.
+diff --git a/gcc/config/sh/sync.md b/gcc/config/sh/sync.md
+index 6f1337b..cff57b8 100644
+--- a/gcc/config/sh/sync.md
++++ b/gcc/config/sh/sync.md
+@@ -240,6 +240,9 @@
+ || (TARGET_SH4A && <MODE>mode == SImode && !TARGET_ATOMIC_STRICT))
+ atomic_insn = gen_atomic_compare_and_swap<mode>_hard (old_val, mem,
+ exp_val, new_val);
++ else if (TARGET_ATOMIC_HARD_CAS && <MODE>mode == SImode)
++ atomic_insn = gen_atomic_compare_and_swap<mode>_cas (old_val, mem,
++ exp_val, new_val);
+ else if (TARGET_ATOMIC_SOFT_GUSA)
+ atomic_insn = gen_atomic_compare_and_swap<mode>_soft_gusa (old_val, mem,
+ exp_val, new_val);
+@@ -306,6 +309,57 @@
+ }
+ [(set_attr "length" "14")])
+
++(define_expand "atomic_compare_and_swapsi_cas"
++ [(set (match_operand:SI 0 "register_operand" "=r")
++ (unspec_volatile:SI
++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
++ (match_operand:SI 2 "register_operand" "r")
++ (match_operand:SI 3 "register_operand" "r")]
++ UNSPECV_CMPXCHG_1))]
++ "TARGET_ATOMIC_HARD_CAS"
++{
++ rtx mem = gen_rtx_REG (SImode, 0);
++ emit_move_insn (mem, force_reg (SImode, XEXP (operands[1], 0)));
++ emit_insn (gen_shj2_cas (operands[0], mem, operands[2], operands[3]));
++ DONE;
++})
++
++(define_insn "shj2_cas"
++ [(set (match_operand:SI 0 "register_operand" "=&r")
++ (unspec_volatile:SI
++ [(match_operand:SI 1 "register_operand" "=r")
++ (match_operand:SI 2 "register_operand" "r")
++ (match_operand:SI 3 "register_operand" "0")]
++ UNSPECV_CMPXCHG_1))
++ (set (reg:SI T_REG)
++ (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3))]
++ "TARGET_ATOMIC_HARD_CAS"
++ "cas.l %2,%0,@%1"
++ [(set_attr "length" "2")]
++)
++
++(define_expand "atomic_compare_and_swapqi_cas"
++ [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
++ (unspec_volatile:SI
++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
++ (match_operand:SI 2 "arith_operand" "rI08")
++ (match_operand:SI 3 "arith_operand" "rI08")]
++ UNSPECV_CMPXCHG_1))]
++ "TARGET_ATOMIC_HARD_CAS"
++{FAIL;}
++)
++
++(define_expand "atomic_compare_and_swaphi_cas"
++ [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
++ (unspec_volatile:SI
++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
++ (match_operand:SI 2 "arith_operand" "rI08")
++ (match_operand:SI 3 "arith_operand" "rI08")]
++ UNSPECV_CMPXCHG_1))]
++ "TARGET_ATOMIC_HARD_CAS"
++{FAIL;}
++)
++
+ ;; The QIHImode llcs patterns modify the address register of the memory
+ ;; operand. In order to express that, we have to open code the memory
+ ;; operand. Initially the insn is expanded like every other atomic insn
+diff --git a/gcc/config/sh/t-sh b/gcc/config/sh/t-sh
+index 348cc0b..8e6bdaf 100644
+--- a/gcc/config/sh/t-sh
++++ b/gcc/config/sh/t-sh
+@@ -52,7 +52,7 @@ MULTILIB_MATCHES = $(shell \
+ m4-single,m4-100-single,m4-200-single,m4-300-single,m4a-single \
+ m4,m4-100,m4-200,m4-300,m4a \
+ m5-32media,m5-compact,m5-32media \
+- m5-32media-nofpu,m5-compact-nofpu,m5-32media-nofpu; do \
++ m5-32media-nofpu,m5-compact-nofpu,m5-32media-nofpu,mj2; do \
+ subst= ; \
+ for lib in `echo $$abi|tr , ' '` ; do \
+ if test "`echo $$multilibs|sed s/$$lib//`" != "$$multilibs"; then \
+@@ -65,9 +65,9 @@ MULTILIB_MATCHES = $(shell \
+
+ # SH1 and SH2A support big endian only.
+ ifeq ($(DEFAULT_ENDIAN),ml)
+-MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG)
++MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG)
+ else
+-MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG)
++MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG)
+ endif
+
+ MULTILIB_OSDIRNAMES = \
+@@ -96,6 +96,7 @@ MULTILIB_OSDIRNAMES = \
+ m5-compact-nofpu=!m5-compact-nofpu $(OTHER_ENDIAN)/m5-compact-nofpu=!$(OTHER_ENDIAN)/m5-compact-nofpu \
+ m5-64media=!m5-64media $(OTHER_ENDIAN)/m5-64media=!$(OTHER_ENDIAN)/m5-64media \
+ m5-64media-nofpu=!m5-64media-nofpu $(OTHER_ENDIAN)/m5-64media-nofpu=!$(OTHER_ENDIAN)/m5-64media-nofpu
++ mj2=!j2
+
+ $(out_object_file): gt-sh.h
+ gt-sh.h : s-gtype ; @true
--- /dev/null
+--- gcc-5.2.0.orig/gcc/config/gnu-user.h 2015-01-05 12:33:28.000000000 +0000
++++ gcc-5.2.0/gcc/config/gnu-user.h 2015-08-25 08:15:18.354957759 +0000
+@@ -42,8 +42,8 @@
+
+ #if defined HAVE_LD_PIE
+ #define GNU_USER_TARGET_STARTFILE_SPEC \
+- "%{!shared: %{pg|p|profile:gcrt1.o%s;pie:Scrt1.o%s;:crt1.o%s}} \
+- crti.o%s %{static:crtbeginT.o%s;shared|pie:crtbeginS.o%s;:crtbegin.o%s} \
++ "%{!shared: %{pg|p|profile:gcrt1.o%s;pie:%{static:rcrt1.o%s;:Scrt1.o%s};:crt1.o%s}} \
++ crti.o%s %{shared|pie:crtbeginS.o%s;static:crtbeginT.o%s;:crtbegin.o%s} \
+ %{fvtable-verify=none:%s; \
+ fvtable-verify=preinit:vtv_start_preinit.o%s; \
+ fvtable-verify=std:vtv_start.o%s}"
+--- gcc-5.2.0.orig/gcc/gcc.c 2015-03-10 09:37:41.000000000 +0000
++++ gcc-5.2.0/gcc/gcc.c 2015-09-30 00:25:33.225927941 +0000
+@@ -739,7 +739,7 @@
+
+ #ifndef LINK_PIE_SPEC
+ #ifdef HAVE_LD_PIE
+-#define LINK_PIE_SPEC "%{pie:-pie} "
++#define LINK_PIE_SPEC "%{pie:-pie %{static:--no-dynamic-linker}} "
+ #else
+ #define LINK_PIE_SPEC "%{pie:} "
+ #endif
--- /dev/null
+diff --git a/gcc/config.gcc b/gcc/config.gcc
+index 3779369..a6d95ca 100644
+--- a/gcc/config.gcc
++++ b/gcc/config.gcc
+@@ -3101,6 +3101,12 @@ case ${target} in
+ ;;
+ esac
+
++case "x${enable_default_pie}" in
++xyes)
++ tm_defines="${tm_defines} ENABLE_DEFAULT_PIE=1"
++ ;;
++esac
++
+ t=
+ all_defaults="abi cpu arch tune schedule float mode fpu divide"
+ for option in $all_defaults
+--- gcc-5.2.0.orig/gcc/gcc.c 2015-03-10 09:37:41.000000000 +0000
++++ gcc-5.2.0/gcc/gcc.c 2015-08-25 07:47:12.895060530 +0000
+@@ -1012,10 +1012,19 @@
+ #define CILK_SELF_SPECS "%{fcilkplus: -pthread}"
+ #endif
+
++/* Default to PIE */
++#ifndef PIE_SELF_SPECS
++#ifdef ENABLE_DEFAULT_PIE
++#define PIE_SELF_SPECS "%{shared|pie|r|nostdlib|nopie|no-pie:;:-pie} %{fpic|fPIC|fpie|fPIE|fno-pic|fno-PIC|fno-pie|fno-PIE|D__KERNEL__:;:-fPIE}"
++#else
++#define PIE_SELF_SPECS ""
++#endif
++#endif
++
+ static const char *const driver_self_specs[] = {
+ "%{fdump-final-insns:-fdump-final-insns=.} %<fdump-final-insns",
+ DRIVER_SELF_SPECS, CONFIGURE_SPECS, GOMP_SELF_SPECS, GTM_SELF_SPECS,
+- CILK_SELF_SPECS
++ CILK_SELF_SPECS, PIE_SELF_SPECS
+ };
+
+ #ifndef OPTION_DEFAULT_SPECS
--- /dev/null
+diff --git a/gcc/config.gcc b/gcc/config.gcc
+index bf26776..ed118f3 100644
+--- a/gcc/config.gcc
++++ b/gcc/config.gcc
+@@ -2621,6 +2621,9 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
+ tm_file="${tm_file} dbxelf.h elfos.h sh/elf.h"
+ case ${target} in
+ sh*-*-linux*) tmake_file="${tmake_file} sh/t-linux"
++ if test x$enable_fdpic = xyes; then
++ tm_defines="$tm_defines FDPIC_DEFAULT=1"
++ fi
+ tm_file="${tm_file} gnu-user.h linux.h glibc-stdint.h sh/linux.h" ;;
+ sh*-*-netbsd*)
+ tm_file="${tm_file} netbsd.h netbsd-elf.h sh/netbsd-elf.h"
+diff --git a/gcc/config/sh/constraints.md b/gcc/config/sh/constraints.md
+index 4d1eb2d..41c88a2 100644
+--- a/gcc/config/sh/constraints.md
++++ b/gcc/config/sh/constraints.md
+@@ -25,6 +25,7 @@
+ ;; Bsc: SCRATCH - for the scratch register in movsi_ie in the
+ ;; fldi0 / fldi0 cases
+ ;; Cxx: Constants other than only CONST_INT
++;; Ccl: call site label
+ ;; Css: signed 16-bit constant, literal or symbolic
+ ;; Csu: unsigned 16-bit constant, literal or symbolic
+ ;; Csy: label or symbol
+@@ -233,6 +234,11 @@ (define_constraint "Bsc"
+ hence mova is being used, hence do not select this pattern."
+ (match_code "scratch"))
+
++(define_constraint "Ccl"
++ "A call site label, for bsrf."
++ (and (match_code "unspec")
++ (match_test "XINT (op, 1) == UNSPEC_CALLER")))
++
+ (define_constraint "Css"
+ "A signed 16-bit constant, literal or symbolic."
+ (and (match_code "const")
+diff --git a/gcc/config/sh/linux.h b/gcc/config/sh/linux.h
+index a9dd43a..5d4dd1f 100644
+--- a/gcc/config/sh/linux.h
++++ b/gcc/config/sh/linux.h
+@@ -69,7 +69,8 @@ along with GCC; see the file COPYING3. If not see
+ #define GLIBC_DYNAMIC_LINKER "/lib/ld-linux.so.2"
+
+ #undef SUBTARGET_LINK_EMUL_SUFFIX
+-#define SUBTARGET_LINK_EMUL_SUFFIX "_linux"
++#define SUBTARGET_LINK_EMUL_SUFFIX "%{mfdpic:_fd;:_linux}"
++
+ #undef SUBTARGET_LINK_SPEC
+ #define SUBTARGET_LINK_SPEC \
+ "%{shared:-shared} \
+diff --git a/gcc/config/sh/sh-c.c b/gcc/config/sh/sh-c.c
+index a98c148..01a12e6 100644
+--- a/gcc/config/sh/sh-c.c
++++ b/gcc/config/sh/sh-c.c
+@@ -141,6 +141,11 @@ sh_cpu_cpp_builtins (cpp_reader* pfile)
+ builtin_define ("__HITACHI__");
+ if (TARGET_FMOVD)
+ builtin_define ("__FMOVD_ENABLED__");
++ if (TARGET_FDPIC)
++ {
++ builtin_define ("__SH_FDPIC__");
++ builtin_define ("__FDPIC__");
++ }
+ builtin_define (TARGET_LITTLE_ENDIAN
+ ? "__LITTLE_ENDIAN__" : "__BIG_ENDIAN__");
+
+diff --git a/gcc/config/sh/sh-mem.cc b/gcc/config/sh/sh-mem.cc
+index 23a7287..4d92f54 100644
+--- a/gcc/config/sh/sh-mem.cc
++++ b/gcc/config/sh/sh-mem.cc
+@@ -123,29 +123,30 @@ expand_block_move (rtx *operands)
+ rtx r4 = gen_rtx_REG (SImode, 4);
+ rtx r5 = gen_rtx_REG (SImode, 5);
+
+- function_symbol (func_addr_rtx, "__movmemSI12_i4", SFUNC_STATIC);
++ rtx lab = function_symbol (func_addr_rtx, "__movmemSI12_i4",
++ SFUNC_STATIC).lab;
+ force_into (XEXP (operands[0], 0), r4);
+ force_into (XEXP (operands[1], 0), r5);
+- emit_insn (gen_block_move_real_i4 (func_addr_rtx));
++ emit_insn (gen_block_move_real_i4 (func_addr_rtx, lab));
+ return true;
+ }
+ else if (! optimize_size)
+ {
+- const char *entry_name;
+ rtx func_addr_rtx = gen_reg_rtx (Pmode);
+- int dwords;
+ rtx r4 = gen_rtx_REG (SImode, 4);
+ rtx r5 = gen_rtx_REG (SImode, 5);
+ rtx r6 = gen_rtx_REG (SImode, 6);
+
+- entry_name = (bytes & 4 ? "__movmem_i4_odd" : "__movmem_i4_even");
+- function_symbol (func_addr_rtx, entry_name, SFUNC_STATIC);
++ rtx lab = function_symbol (func_addr_rtx, bytes & 4
++ ? "__movmem_i4_odd"
++ : "__movmem_i4_even",
++ SFUNC_STATIC).lab;
+ force_into (XEXP (operands[0], 0), r4);
+ force_into (XEXP (operands[1], 0), r5);
+
+- dwords = bytes >> 3;
++ int dwords = bytes >> 3;
+ emit_insn (gen_move_insn (r6, GEN_INT (dwords - 1)));
+- emit_insn (gen_block_lump_real_i4 (func_addr_rtx));
++ emit_insn (gen_block_lump_real_i4 (func_addr_rtx, lab));
+ return true;
+ }
+ else
+@@ -159,10 +160,10 @@ expand_block_move (rtx *operands)
+ rtx r5 = gen_rtx_REG (SImode, 5);
+
+ sprintf (entry, "__movmemSI%d", bytes);
+- function_symbol (func_addr_rtx, entry, SFUNC_STATIC);
++ rtx lab = function_symbol (func_addr_rtx, entry, SFUNC_STATIC).lab;
+ force_into (XEXP (operands[0], 0), r4);
+ force_into (XEXP (operands[1], 0), r5);
+- emit_insn (gen_block_move_real (func_addr_rtx));
++ emit_insn (gen_block_move_real (func_addr_rtx, lab));
+ return true;
+ }
+
+@@ -176,7 +177,7 @@ expand_block_move (rtx *operands)
+ rtx r5 = gen_rtx_REG (SImode, 5);
+ rtx r6 = gen_rtx_REG (SImode, 6);
+
+- function_symbol (func_addr_rtx, "__movmem", SFUNC_STATIC);
++ rtx lab = function_symbol (func_addr_rtx, "__movmem", SFUNC_STATIC).lab;
+ force_into (XEXP (operands[0], 0), r4);
+ force_into (XEXP (operands[1], 0), r5);
+
+@@ -189,7 +190,7 @@ expand_block_move (rtx *operands)
+ final_switch = 16 - ((bytes / 4) % 16);
+ while_loop = ((bytes / 4) / 16 - 1) * 16;
+ emit_insn (gen_move_insn (r6, GEN_INT (while_loop + final_switch)));
+- emit_insn (gen_block_lump_real (func_addr_rtx));
++ emit_insn (gen_block_lump_real (func_addr_rtx, lab));
+ return true;
+ }
+
+diff --git a/gcc/config/sh/sh-protos.h b/gcc/config/sh/sh-protos.h
+index f94459f..c64a948 100644
+--- a/gcc/config/sh/sh-protos.h
++++ b/gcc/config/sh/sh-protos.h
+@@ -377,7 +377,19 @@ extern void fpscr_set_from_mem (int, HARD_REG_SET);
+ extern void sh_pr_interrupt (struct cpp_reader *);
+ extern void sh_pr_trapa (struct cpp_reader *);
+ extern void sh_pr_nosave_low_regs (struct cpp_reader *);
+-extern rtx function_symbol (rtx, const char *, enum sh_function_kind);
++
++struct function_symbol_result
++{
++ function_symbol_result (void) : sym (NULL), lab (NULL) { }
++ function_symbol_result (rtx s, rtx l) : sym (s), lab (l) { }
++
++ rtx sym;
++ rtx lab;
++};
++
++extern function_symbol_result function_symbol (rtx, const char *,
++ sh_function_kind);
++extern rtx sh_get_fdpic_reg_initial_val (void);
+ extern rtx sh_get_pr_initial_val (void);
+
+ extern void sh_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree,
+@@ -396,4 +408,5 @@ extern bool sh_hard_regno_mode_ok (unsigned int, machine_mode);
+ extern machine_mode sh_hard_regno_caller_save_mode (unsigned int, unsigned int,
+ machine_mode);
+ extern bool sh_can_use_simple_return_p (void);
++extern rtx sh_load_function_descriptor (rtx);
+ #endif /* ! GCC_SH_PROTOS_H */
+diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
+index 904201b..e6a0b1e 100644
+--- a/gcc/config/sh/sh.c
++++ b/gcc/config/sh/sh.c
+@@ -268,6 +268,7 @@ static rtx sh_expand_builtin (tree, rtx, rtx, machine_mode, int);
+ static void sh_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
+ HOST_WIDE_INT, tree);
+ static void sh_file_start (void);
++static bool sh_assemble_integer (rtx, unsigned int, int);
+ static bool flow_dependent_p (rtx, rtx);
+ static void flow_dependent_p_1 (rtx, const_rtx, void *);
+ static int shiftcosts (rtx);
+@@ -276,6 +277,7 @@ static int addsubcosts (rtx);
+ static int multcosts (rtx);
+ static bool unspec_caller_rtx_p (rtx);
+ static bool sh_cannot_copy_insn_p (rtx_insn *);
++static bool sh_cannot_force_const_mem_p (machine_mode, rtx);
+ static bool sh_rtx_costs (rtx, int, int, int, int *, bool);
+ static int sh_address_cost (rtx, machine_mode, addr_space_t, bool);
+ static int sh_pr_n_sets (void);
+@@ -421,6 +423,9 @@ static const struct attribute_spec sh_attribute_table[] =
+ #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
+ #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
+
++#undef TARGET_ASM_INTEGER
++#define TARGET_ASM_INTEGER sh_assemble_integer
++
+ #undef TARGET_REGISTER_MOVE_COST
+ #define TARGET_REGISTER_MOVE_COST sh_register_move_cost
+
+@@ -679,6 +684,9 @@ static const struct attribute_spec sh_attribute_table[] =
+ #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
+ #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 0x80
+
++#undef TARGET_CANNOT_FORCE_CONST_MEM
++#define TARGET_CANNOT_FORCE_CONST_MEM sh_cannot_force_const_mem_p
++
+ struct gcc_target targetm = TARGET_INITIALIZER;
+ \f
+
+@@ -996,6 +1004,13 @@ sh_option_override (void)
+ if (! global_options_set.x_TARGET_ZDCBRANCH && TARGET_HARD_SH4)
+ TARGET_ZDCBRANCH = 1;
+
++ /* FDPIC code is a special form of PIC, and the vast majority of code
++ generation constraints that apply to PIC also apply to FDPIC, so we
++ set flag_pic to avoid the need to check TARGET_FDPIC everywhere
++ flag_pic is checked. */
++ if (TARGET_FDPIC && !flag_pic)
++ flag_pic = 2;
++
+ for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
+ if (! VALID_REGISTER_P (regno))
+ sh_register_names[regno][0] = '\0';
+@@ -1687,6 +1702,14 @@ sh_asm_output_addr_const_extra (FILE *file, rtx x)
+ output_addr_const (file, XVECEXP (x, 0, 1));
+ fputs ("-.)", file);
+ break;
++ case UNSPEC_GOTFUNCDESC:
++ output_addr_const (file, XVECEXP (x, 0, 0));
++ fputs ("@GOTFUNCDESC", file);
++ break;
++ case UNSPEC_GOTOFFFUNCDESC:
++ output_addr_const (file, XVECEXP (x, 0, 0));
++ fputs ("@GOTOFFFUNCDESC", file);
++ break;
+ default:
+ return false;
+ }
+@@ -1871,6 +1894,9 @@ prepare_move_operands (rtx operands[], machine_mode mode)
+ {
+ case TLS_MODEL_GLOBAL_DYNAMIC:
+ tga_ret = gen_rtx_REG (Pmode, R0_REG);
++ if (TARGET_FDPIC)
++ emit_move_insn (gen_rtx_REG (Pmode, PIC_REG),
++ sh_get_fdpic_reg_initial_val ());
+ emit_call_insn (gen_tls_global_dynamic (tga_ret, op1));
+ tmp = gen_reg_rtx (Pmode);
+ emit_move_insn (tmp, tga_ret);
+@@ -1879,6 +1905,9 @@ prepare_move_operands (rtx operands[], machine_mode mode)
+
+ case TLS_MODEL_LOCAL_DYNAMIC:
+ tga_ret = gen_rtx_REG (Pmode, R0_REG);
++ if (TARGET_FDPIC)
++ emit_move_insn (gen_rtx_REG (Pmode, PIC_REG),
++ sh_get_fdpic_reg_initial_val ());
+ emit_call_insn (gen_tls_local_dynamic (tga_ret, op1));
+
+ tmp = gen_reg_rtx (Pmode);
+@@ -1896,6 +1925,9 @@ prepare_move_operands (rtx operands[], machine_mode mode)
+ case TLS_MODEL_INITIAL_EXEC:
+ tga_op1 = !can_create_pseudo_p () ? op0 : gen_reg_rtx (Pmode);
+ tmp = gen_sym2GOTTPOFF (op1);
++ if (TARGET_FDPIC)
++ emit_move_insn (gen_rtx_REG (Pmode, PIC_REG),
++ sh_get_fdpic_reg_initial_val ());
+ emit_insn (gen_tls_initial_exec (tga_op1, tmp));
+ op1 = tga_op1;
+ break;
+@@ -1922,6 +1954,22 @@ prepare_move_operands (rtx operands[], machine_mode mode)
+ operands[1] = op1;
+ }
+ }
++
++ if (SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P)
++ {
++ rtx base, offset;
++ split_const (operands[1], &base, &offset);
++
++ if (GET_CODE (base) == SYMBOL_REF
++ && !offset_within_block_p (base, INTVAL (offset)))
++ {
++ rtx tmp = can_create_pseudo_p () ? gen_reg_rtx (mode) : operands[0];
++ emit_move_insn (tmp, base);
++ if (!arith_operand (offset, mode))
++ offset = force_reg (mode, offset);
++ emit_insn (gen_add3_insn (operands[0], tmp, offset));
++ }
++ }
+ }
+
+ /* Implement the canonicalize_comparison target hook for the combine
+@@ -3026,6 +3074,24 @@ sh_file_start (void)
+ }
+ }
+ \f
++/* Implementation of TARGET_ASM_INTEGER for SH. Pointers to functions
++ need to be output as pointers to function descriptors for
++ FDPIC. */
++
++static bool
++sh_assemble_integer (rtx value, unsigned int size, int aligned_p)
++{
++ if (TARGET_FDPIC && size == UNITS_PER_WORD
++ && GET_CODE (value) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (value))
++ {
++ fputs ("\t.long\t", asm_out_file);
++ output_addr_const (asm_out_file, value);
++ fputs ("@FUNCDESC\n", asm_out_file);
++ return true;
++ }
++ return default_assemble_integer (value, size, aligned_p);
++}
++\f
+ /* Check if PAT includes UNSPEC_CALLER unspec pattern. */
+ static bool
+ unspec_caller_rtx_p (rtx pat)
+@@ -3061,6 +3127,17 @@ sh_cannot_copy_insn_p (rtx_insn *insn)
+ return false;
+
+ pat = PATTERN (insn);
++
++ if (GET_CODE (pat) == CLOBBER || GET_CODE (pat) == USE)
++ return false;
++
++ if (TARGET_FDPIC && GET_CODE (pat) == PARALLEL)
++ {
++ rtx t = XVECEXP (pat, 0, XVECLEN (pat, 0) - 1);
++ if (GET_CODE (t) == USE && unspec_caller_rtx_p (XEXP (t, 0)))
++ return true;
++ }
++
+ if (GET_CODE (pat) != SET)
+ return false;
+ pat = SET_SRC (pat);
+@@ -4102,8 +4179,8 @@ expand_ashiftrt (rtx *operands)
+ /* Load the value into an arg reg and call a helper. */
+ emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
+ sprintf (func, "__ashiftrt_r4_%d", value);
+- function_symbol (wrk, func, SFUNC_STATIC);
+- emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk));
++ rtx lab = function_symbol (wrk, func, SFUNC_STATIC).lab;
++ emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk, lab));
+ emit_move_insn (operands[0], gen_rtx_REG (SImode, 4));
+ return true;
+ }
+@@ -7954,7 +8031,8 @@ sh_expand_prologue (void)
+ stack_usage += d;
+ }
+
+- if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
++ if (flag_pic && !TARGET_FDPIC
++ && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
+ emit_insn (gen_GOTaddr2picreg (const0_rtx));
+
+ if (SHMEDIA_REGS_STACK_ADJUST ())
+@@ -10458,7 +10536,9 @@ nonpic_symbol_mentioned_p (rtx x)
+ || XINT (x, 1) == UNSPEC_PLT
+ || XINT (x, 1) == UNSPEC_PCREL
+ || XINT (x, 1) == UNSPEC_SYMOFF
+- || XINT (x, 1) == UNSPEC_PCREL_SYMOFF))
++ || XINT (x, 1) == UNSPEC_PCREL_SYMOFF
++ || XINT (x, 1) == UNSPEC_GOTFUNCDESC
++ || XINT (x, 1) == UNSPEC_GOTOFFFUNCDESC))
+ return false;
+
+ fmt = GET_RTX_FORMAT (GET_CODE (x));
+@@ -10493,7 +10573,26 @@ legitimize_pic_address (rtx orig, machine_mode mode ATTRIBUTE_UNUSED,
+ if (reg == NULL_RTX)
+ reg = gen_reg_rtx (Pmode);
+
+- emit_insn (gen_symGOTOFF2reg (reg, orig));
++ if (TARGET_FDPIC
++ && GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (orig))
++ {
++ /* Weak functions may be NULL which doesn't work with
++ GOTOFFFUNCDESC because the runtime offset is not known. */
++ if (SYMBOL_REF_WEAK (orig))
++ emit_insn (gen_symGOTFUNCDESC2reg (reg, orig));
++ else
++ emit_insn (gen_symGOTOFFFUNCDESC2reg (reg, orig));
++ }
++ else if (TARGET_FDPIC
++ && (GET_CODE (orig) == LABEL_REF
++ || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_DECL (orig)
++ && (TREE_READONLY (SYMBOL_REF_DECL (orig))
++ || SYMBOL_REF_EXTERNAL_P (orig)
++ || DECL_SECTION_NAME(SYMBOL_REF_DECL (orig))))))
++ /* In FDPIC, GOTOFF can only be used for writable data. */
++ emit_insn (gen_symGOT2reg (reg, orig));
++ else
++ emit_insn (gen_symGOTOFF2reg (reg, orig));
+ return reg;
+ }
+ else if (GET_CODE (orig) == SYMBOL_REF)
+@@ -10501,7 +10600,10 @@ legitimize_pic_address (rtx orig, machine_mode mode ATTRIBUTE_UNUSED,
+ if (reg == NULL_RTX)
+ reg = gen_reg_rtx (Pmode);
+
+- emit_insn (gen_symGOT2reg (reg, orig));
++ if (TARGET_FDPIC && SYMBOL_REF_FUNCTION_P (orig))
++ emit_insn (gen_symGOTFUNCDESC2reg (reg, orig));
++ else
++ emit_insn (gen_symGOT2reg (reg, orig));
+ return reg;
+ }
+ return orig;
+@@ -11539,8 +11641,39 @@ sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED)
+ 5 0008 00000000 l1: .long area
+ 6 000c 00000000 l2: .long function
+
++ FDPIC needs a form that includes a function descriptor and
++ code to load the GOT register:
++ 0 0000 00000000 .long l0
++ 1 0004 00000000 .long gotval
++ 2 0008 D302 l0: mov.l l1,r3
++ 3 000a D203 mov.l l2,r2
++ 4 000c 6122 mov.l @r2,r1
++ 5 000e 5C21 mov.l @(4,r2),r12
++ 6 0010 412B jmp @r1
++ 7 0012 0009 nop
++ 8 0014 00000000 l1: .long area
++ 9 0018 00000000 l2: .long function
++
+ SH5 (compact) uses r1 instead of r3 for the static chain. */
+
++/* Emit insns to store a value at memory address + offset. */
++static void
++sh_emit_storesi (rtx addr, HOST_WIDE_INT offset, rtx value)
++{
++ gcc_assert ((offset & 3) == 0);
++ emit_move_insn (offset == 0
++ ? change_address (addr, SImode, NULL_RTX)
++ : adjust_address (addr, SImode, offset), value);
++}
++
++/* Emit insns to store w0 at addr + offset and w1 at addr + offset + 2. */
++static void
++sh_emit_storehi (rtx addr, HOST_WIDE_INT offset, uint16_t w0, uint16_t w1)
++{
++ sh_emit_storesi (addr, offset, gen_int_mode (TARGET_LITTLE_ENDIAN
++ ? (w0 | (w1 << 16))
++ : (w1 | (w0 << 16)), SImode));
++}
+
+ /* Emit RTL insns to initialize the variable parts of a trampoline.
+ FNADDR is an RTX for the address of the function's pure code.
+@@ -11675,20 +11808,34 @@ sh_trampoline_init (rtx tramp_mem, tree fndecl, rtx cxt)
+ emit_insn (gen_initialize_trampoline (tramp, cxt, fnaddr));
+ return;
+ }
+- emit_move_insn (change_address (tramp_mem, SImode, NULL_RTX),
+- gen_int_mode (TARGET_LITTLE_ENDIAN ? 0xd301d202 : 0xd202d301,
+- SImode));
+- emit_move_insn (adjust_address (tramp_mem, SImode, 4),
+- gen_int_mode (TARGET_LITTLE_ENDIAN ? 0x0009422b : 0x422b0009,
+- SImode));
+- emit_move_insn (adjust_address (tramp_mem, SImode, 8), cxt);
+- emit_move_insn (adjust_address (tramp_mem, SImode, 12), fnaddr);
++ if (TARGET_FDPIC)
++ {
++ rtx a = force_reg (Pmode, plus_constant (Pmode, XEXP (tramp_mem, 0), 8));
++
++ sh_emit_storesi (tramp_mem, 0, a);
++ sh_emit_storesi (tramp_mem, 4, sh_get_fdpic_reg_initial_val ());
++
++ sh_emit_storehi (tramp_mem, 8, 0xd302, 0xd203);
++ sh_emit_storehi (tramp_mem, 12, 0x6122, 0x5c21);
++ sh_emit_storehi (tramp_mem, 16, 0x412b, 0x0009);
++
++ sh_emit_storesi (tramp_mem, 20, cxt);
++ sh_emit_storesi (tramp_mem, 24, fnaddr);
++ }
++ else
++ {
++ sh_emit_storehi (tramp_mem, 0, 0xd202, 0xd301);
++ sh_emit_storehi (tramp_mem, 4, 0x422b, 0x0009);
++
++ sh_emit_storesi (tramp_mem, 8, cxt);
++ sh_emit_storesi (tramp_mem, 12, fnaddr);
++ }
+ if (TARGET_HARD_SH4 || TARGET_SH5)
+ {
+ if (!TARGET_INLINE_IC_INVALIDATE
+ || (!(TARGET_SH4A || TARGET_SH4_300) && TARGET_USERMODE))
+ emit_library_call (function_symbol (NULL, "__ic_invalidate",
+- FUNCTION_ORDINARY),
++ FUNCTION_ORDINARY).sym,
+ LCT_NORMAL, VOIDmode, 1, tramp, SImode);
+ else
+ emit_insn (gen_ic_invalidate_line (tramp));
+@@ -11718,7 +11865,7 @@ sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
+ && (! TARGET_SHCOMPACT
+ || crtl->args.info.stack_regs == 0)
+ && ! sh_cfun_interrupt_handler_p ()
+- && (! flag_pic
++ && (! flag_pic || TARGET_FDPIC
+ || (decl && ! (TREE_PUBLIC (decl) || DECL_WEAK (decl)))
+ || (decl && DECL_VISIBILITY (decl) != VISIBILITY_DEFAULT)));
+ }
+@@ -11732,7 +11879,7 @@ sh_expand_sym_label2reg (rtx reg, rtx sym, rtx lab, bool sibcall_p)
+
+ if (!is_weak && SYMBOL_REF_LOCAL_P (sym))
+ emit_insn (gen_sym_label2reg (reg, sym, lab));
+- else if (sibcall_p)
++ else if (sibcall_p && SYMBOL_REF_LOCAL_P (sym))
+ emit_insn (gen_symPCREL_label2reg (reg, sym, lab));
+ else
+ emit_insn (gen_symPLT_label2reg (reg, sym, lab));
+@@ -12733,8 +12880,16 @@ sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
+ #endif
+ if (TARGET_SH2 && flag_pic)
+ {
+- sibcall = gen_sibcall_pcrel (funexp, const0_rtx);
+- XEXP (XVECEXP (sibcall, 0, 2), 0) = scratch2;
++ if (TARGET_FDPIC)
++ {
++ sibcall = gen_sibcall_pcrel_fdpic (funexp, const0_rtx);
++ XEXP (XVECEXP (sibcall, 0, 3), 0) = scratch2;
++ }
++ else
++ {
++ sibcall = gen_sibcall_pcrel (funexp, const0_rtx);
++ XEXP (XVECEXP (sibcall, 0, 2), 0) = scratch2;
++ }
+ }
+ else
+ {
+@@ -12775,17 +12930,25 @@ sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
+ epilogue_completed = 0;
+ }
+
+-rtx
+-function_symbol (rtx target, const char *name, enum sh_function_kind kind)
+-{
+- rtx sym;
++/* Return an RTX pair for the address and call site label of a function
++ NAME of kind KIND, placing the result in TARGET if not NULL. For
++ SFUNC_STATIC, if FDPIC, the LAB member of result will be set to
++ (const_int 0) if jsr should be used, or a label_ref if bsrf should
++ be used. For FDPIC, both SFUNC_GOT and SFUNC_STATIC will return the
++ address of the function itself, not a function descriptor, so they
++ can only be used with functions not using the FDPIC register that
++ are known to be called directory without a PLT entry. */
+
++function_symbol_result
++function_symbol (rtx target, const char *name, sh_function_kind kind)
++{
+ /* If this is not an ordinary function, the name usually comes from a
+ string literal or an sprintf buffer. Make sure we use the same
+ string consistently, so that cse will be able to unify address loads. */
+ if (kind != FUNCTION_ORDINARY)
+ name = IDENTIFIER_POINTER (get_identifier (name));
+- sym = gen_rtx_SYMBOL_REF (Pmode, name);
++ rtx sym = gen_rtx_SYMBOL_REF (Pmode, name);
++ rtx lab = const0_rtx;
+ SYMBOL_REF_FLAGS (sym) = SYMBOL_FLAG_FUNCTION;
+ if (flag_pic)
+ switch (kind)
+@@ -12802,14 +12965,25 @@ function_symbol (rtx target, const char *name, enum sh_function_kind kind)
+ }
+ case SFUNC_STATIC:
+ {
+- /* ??? To allow cse to work, we use GOTOFF relocations.
+- We could add combiner patterns to transform this into
+- straight pc-relative calls with sym2PIC / bsrf when
+- label load and function call are still 1:1 and in the
+- same basic block during combine. */
+ rtx reg = target ? target : gen_reg_rtx (Pmode);
+
+- emit_insn (gen_symGOTOFF2reg (reg, sym));
++ if (TARGET_FDPIC)
++ {
++ /* We use PC-relative calls, since GOTOFF can only refer
++ to writable data. This works along with sh_sfunc_call. */
++ lab = PATTERN (gen_call_site ());
++ emit_insn (gen_sym_label2reg (reg, sym, lab));
++ }
++ else
++ {
++ /* ??? To allow cse to work, we use GOTOFF relocations.
++ we could add combiner patterns to transform this into
++ straight pc-relative calls with sym2PIC / bsrf when
++ label load and function call are still 1:1 and in the
++ same basic block during combine. */
++ emit_insn (gen_symGOTOFF2reg (reg, sym));
++ }
++
+ sym = reg;
+ break;
+ }
+@@ -12817,9 +12991,9 @@ function_symbol (rtx target, const char *name, enum sh_function_kind kind)
+ if (target && sym != target)
+ {
+ emit_move_insn (target, sym);
+- return target;
++ return function_symbol_result (target, lab);
+ }
+- return sym;
++ return function_symbol_result (sym, lab);
+ }
+
+ /* Find the number of a general purpose register in S. */
+@@ -13432,6 +13606,12 @@ sh_conditional_register_usage (void)
+ fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
+ call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
+ }
++ if (TARGET_FDPIC)
++ {
++ fixed_regs[PIC_REG] = 1;
++ call_used_regs[PIC_REG] = 1;
++ call_really_used_regs[PIC_REG] = 1;
++ }
+ /* Renesas saves and restores mac registers on call. */
+ if (TARGET_HITACHI && ! TARGET_NOMACSAVE)
+ {
+@@ -13460,14 +13640,32 @@ sh_conditional_register_usage (void)
+ static bool
+ sh_legitimate_constant_p (machine_mode mode, rtx x)
+ {
+- return (TARGET_SHMEDIA
+- ? ((mode != DFmode && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
+- || x == CONST0_RTX (mode)
+- || !TARGET_SHMEDIA_FPU
+- || TARGET_SHMEDIA64)
+- : (GET_CODE (x) != CONST_DOUBLE
+- || mode == DFmode || mode == SFmode
+- || mode == DImode || GET_MODE (x) == VOIDmode));
++ if (SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P)
++ {
++ rtx base, offset;
++ split_const (x, &base, &offset);
++
++ if (GET_CODE (base) == SYMBOL_REF
++ && !offset_within_block_p (base, INTVAL (offset)))
++ return false;
++ }
++
++ if (TARGET_FDPIC
++ && (SYMBOLIC_CONST_P (x)
++ || (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
++ && SYMBOLIC_CONST_P (XEXP (XEXP (x, 0), 0)))))
++ return false;
++
++ if (TARGET_SHMEDIA
++ && ((mode != DFmode && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
++ || x == CONST0_RTX (mode)
++ || !TARGET_SHMEDIA_FPU
++ || TARGET_SHMEDIA64))
++ return false;
++
++ return GET_CODE (x) != CONST_DOUBLE
++ || mode == DFmode || mode == SFmode
++ || mode == DImode || GET_MODE (x) == VOIDmode;
+ }
+
+ enum sh_divide_strategy_e sh_div_strategy = SH_DIV_STRATEGY_DEFAULT;
+@@ -14558,4 +14756,41 @@ sh_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size,
+ }
+ }
+
++bool
++sh_cannot_force_const_mem_p (machine_mode mode ATTRIBUTE_UNUSED,
++ rtx x ATTRIBUTE_UNUSED)
++{
++ return TARGET_FDPIC;
++}
++
++/* Emit insns to load the function address from FUNCDESC (an FDPIC
++ function descriptor) into r1 and the GOT address into r12,
++ returning an rtx for r1. */
++
++rtx
++sh_load_function_descriptor (rtx funcdesc)
++{
++ rtx r1 = gen_rtx_REG (Pmode, R1_REG);
++ rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
++ rtx fnaddr = gen_rtx_MEM (Pmode, funcdesc);
++ rtx gotaddr = gen_rtx_MEM (Pmode, plus_constant (Pmode, funcdesc, 4));
++
++ emit_move_insn (r1, fnaddr);
++ /* The ABI requires the entry point address to be loaded first, so
++ prevent the load from being moved after that of the GOT
++ address. */
++ emit_insn (gen_blockage ());
++ emit_move_insn (pic_reg, gotaddr);
++ return r1;
++}
++
++/* Return an rtx holding the initial value of the FDPIC register (the
++ FDPIC pointer passed in from the caller). */
++
++rtx
++sh_get_fdpic_reg_initial_val (void)
++{
++ return get_hard_reg_initial_val (Pmode, PIC_REG);
++}
++
+ #include "gt-sh.h"
+diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
+index aafcf28..e232179 100644
+--- a/gcc/config/sh/sh.h
++++ b/gcc/config/sh/sh.h
+@@ -321,7 +321,7 @@ extern int code_for_indirect_jump_scratch;
+ #endif
+
+ #ifndef SUBTARGET_ASM_SPEC
+-#define SUBTARGET_ASM_SPEC ""
++#define SUBTARGET_ASM_SPEC "%{mfdpic:--fdpic}"
+ #endif
+
+ #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN
+@@ -349,7 +349,7 @@ extern int code_for_indirect_jump_scratch;
+ #define ASM_ISA_DEFAULT_SPEC ""
+ #endif /* MASK_SH5 */
+
+-#define SUBTARGET_LINK_EMUL_SUFFIX ""
++#define SUBTARGET_LINK_EMUL_SUFFIX "%{mfdpic:_fd}"
+ #define SUBTARGET_LINK_SPEC ""
+
+ /* Go via SH_LINK_SPEC to avoid code replication. */
+@@ -383,8 +383,18 @@ extern int code_for_indirect_jump_scratch;
+ "%{m2a*:%eSH2a does not support little-endian}}"
+ #endif
+
++#ifdef FDPIC_DEFAULT
++#define FDPIC_SELF_SPECS "%{!mno-fdpic:-mfdpic}"
++#else
++#define FDPIC_SELF_SPECS
++#endif
++
+ #undef DRIVER_SELF_SPECS
+-#define DRIVER_SELF_SPECS UNSUPPORTED_SH2A
++#define DRIVER_SELF_SPECS UNSUPPORTED_SH2A SUBTARGET_DRIVER_SELF_SPECS \
++ FDPIC_SELF_SPECS
++
++#undef SUBTARGET_DRIVER_SELF_SPECS
++#define SUBTARGET_DRIVER_SELF_SPECS
+
+ #define ASSEMBLER_DIALECT assembler_dialect
+
+@@ -942,6 +952,10 @@ extern char sh_additional_register_names[ADDREGNAMES_SIZE] \
+ code access to data items. */
+ #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM)
+
++/* For FDPIC, the FDPIC register is call-clobbered (otherwise PLT
++ entries would need to handle saving and restoring it). */
++#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED TARGET_FDPIC
++
+ #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
+
+ /* Definitions for register eliminations.
+@@ -1566,7 +1580,8 @@ struct sh_args {
+ 6 000c 00000000 l2: .long function */
+
+ /* Length in units of the trampoline for entering a nested function. */
+-#define TRAMPOLINE_SIZE (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : 16)
++#define TRAMPOLINE_SIZE \
++ (TARGET_SHMEDIA64 ? 40 : TARGET_SH5 ? 24 : TARGET_FDPIC ? 32 : 16)
+
+ /* Alignment required for a trampoline in bits. */
+ #define TRAMPOLINE_ALIGNMENT \
+@@ -1622,6 +1637,10 @@ struct sh_args {
+ || GENERAL_REGISTER_P ((unsigned) reg_renumber[(REGNO)])) \
+ : (REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG)
+
++/* True if SYMBOL + OFFSET constants must refer to something within
++ SYMBOL's section. */
++#define SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P TARGET_FDPIC
++
+ /* Maximum number of registers that can appear in a valid memory
+ address. */
+ #define MAX_REGS_PER_ADDRESS 2
+@@ -2262,9 +2281,11 @@ extern int current_function_interrupt;
+ /* We have to distinguish between code and data, so that we apply
+ datalabel where and only where appropriate. Use sdataN for data. */
+ #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
+- ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
+- | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr) \
+- | ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)))
++ ((TARGET_FDPIC \
++ ? ((GLOBAL) ? DW_EH_PE_indirect | DW_EH_PE_datarel : DW_EH_PE_pcrel) \
++ : ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
++ | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr))) \
++ | ((CODE) ? 0 : (TARGET_SHMEDIA64 ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)))
+
+ /* Handle special EH pointer encodings. Absolute, pc-relative, and
+ indirect are handled automatically. */
+@@ -2277,6 +2298,17 @@ extern int current_function_interrupt;
+ SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
+ if (0) goto DONE; \
+ } \
++ if (TARGET_FDPIC \
++ && ((ENCODING) & 0xf0) == (DW_EH_PE_indirect | DW_EH_PE_datarel)) \
++ { \
++ fputs ("\t.ualong ", FILE); \
++ output_addr_const (FILE, ADDR); \
++ if (GET_CODE (ADDR) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (ADDR)) \
++ fputs ("@GOTFUNCDESC", FILE); \
++ else \
++ fputs ("@GOT", FILE); \
++ goto DONE; \
++ } \
+ } while (0)
+
+ #if (defined CRT_BEGIN || defined CRT_END) && ! __SHMEDIA__
+diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md
+index d758e3b..45c9995 100644
+--- a/gcc/config/sh/sh.md
++++ b/gcc/config/sh/sh.md
+@@ -170,6 +170,9 @@ (define_c_enum "unspec" [
+ UNSPEC_SYMOFF
+ ;; (unspec [OFFSET ANCHOR] UNSPEC_PCREL_SYMOFF) == OFFSET - (ANCHOR - .).
+ UNSPEC_PCREL_SYMOFF
++ ;; For FDPIC
++ UNSPEC_GOTFUNCDESC
++ UNSPEC_GOTOFFFUNCDESC
+ ;; Misc builtins
+ UNSPEC_BUILTIN_STRLEN
+ ])
+@@ -2591,15 +2594,18 @@ (define_insn "udivsi3_sh2a"
+ ;; This reload would clobber the value in r0 we are trying to store.
+ ;; If we let reload allocate r0, then this problem can never happen.
+ (define_insn "udivsi3_i1"
+- [(set (match_operand:SI 0 "register_operand" "=z")
++ [(set (match_operand:SI 0 "register_operand" "=z,z")
+ (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
+ (clobber (reg:SI T_REG))
+ (clobber (reg:SI PR_REG))
+ (clobber (reg:SI R1_REG))
+ (clobber (reg:SI R4_REG))
+- (use (match_operand:SI 1 "arith_reg_operand" "r"))]
++ (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
++ (use (match_operand 2 "" "Z,Ccl"))]
+ "TARGET_SH1 && TARGET_DIVIDE_CALL_DIV1"
+- "jsr @%1%#"
++ "@
++ jsr @%1%#
++ bsrf %1\n%O2:%#"
+ [(set_attr "type" "sfunc")
+ (set_attr "needs_delay_slot" "yes")])
+
+@@ -2648,7 +2654,7 @@ (define_expand "udivsi3_i4_media"
+ })
+
+ (define_insn "udivsi3_i4"
+- [(set (match_operand:SI 0 "register_operand" "=y")
++ [(set (match_operand:SI 0 "register_operand" "=y,y")
+ (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
+ (clobber (reg:SI T_REG))
+ (clobber (reg:SI PR_REG))
+@@ -2660,16 +2666,19 @@ (define_insn "udivsi3_i4"
+ (clobber (reg:SI R4_REG))
+ (clobber (reg:SI R5_REG))
+ (clobber (reg:SI FPSCR_STAT_REG))
+- (use (match_operand:SI 1 "arith_reg_operand" "r"))
++ (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
++ (use (match_operand 2 "" "Z,Ccl"))
+ (use (reg:SI FPSCR_MODES_REG))]
+ "TARGET_FPU_DOUBLE && ! TARGET_FPU_SINGLE"
+- "jsr @%1%#"
++ "@
++ jsr @%1%#
++ bsrf %1\n%O2:%#"
+ [(set_attr "type" "sfunc")
+ (set_attr "fp_mode" "double")
+ (set_attr "needs_delay_slot" "yes")])
+
+ (define_insn "udivsi3_i4_single"
+- [(set (match_operand:SI 0 "register_operand" "=y")
++ [(set (match_operand:SI 0 "register_operand" "=y,y")
+ (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
+ (clobber (reg:SI T_REG))
+ (clobber (reg:SI PR_REG))
+@@ -2680,10 +2689,13 @@ (define_insn "udivsi3_i4_single"
+ (clobber (reg:SI R1_REG))
+ (clobber (reg:SI R4_REG))
+ (clobber (reg:SI R5_REG))
+- (use (match_operand:SI 1 "arith_reg_operand" "r"))]
++ (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
++ (use (match_operand 2 "" "Z,Ccl"))]
+ "(TARGET_FPU_SINGLE_ONLY || TARGET_FPU_DOUBLE || TARGET_SHCOMPACT)
+ && TARGET_FPU_SINGLE"
+- "jsr @%1%#"
++ "@
++ jsr @%1%#
++ bsrf %1\n%O2:%#"
+ [(set_attr "type" "sfunc")
+ (set_attr "needs_delay_slot" "yes")])
+
+@@ -2742,11 +2754,11 @@ (define_expand "udivsi3"
+ }
+ else if (TARGET_DIVIDE_CALL_FP)
+ {
+- function_symbol (operands[3], "__udivsi3_i4", SFUNC_STATIC);
++ rtx lab = function_symbol (operands[3], "__udivsi3_i4", SFUNC_STATIC).lab;
+ if (TARGET_FPU_SINGLE)
+- last = gen_udivsi3_i4_single (operands[0], operands[3]);
++ last = gen_udivsi3_i4_single (operands[0], operands[3], lab);
+ else
+- last = gen_udivsi3_i4 (operands[0], operands[3]);
++ last = gen_udivsi3_i4 (operands[0], operands[3], lab);
+ }
+ else if (TARGET_SHMEDIA_FPU)
+ {
+@@ -2771,14 +2783,14 @@ (define_expand "udivsi3"
+ if (TARGET_SHMEDIA)
+ last = gen_udivsi3_i1_media (operands[0], operands[3]);
+ else if (TARGET_FPU_ANY)
+- last = gen_udivsi3_i4_single (operands[0], operands[3]);
++ last = gen_udivsi3_i4_single (operands[0], operands[3], const0_rtx);
+ else
+- last = gen_udivsi3_i1 (operands[0], operands[3]);
++ last = gen_udivsi3_i1 (operands[0], operands[3], const0_rtx);
+ }
+ else
+ {
+- function_symbol (operands[3], "__udivsi3", SFUNC_STATIC);
+- last = gen_udivsi3_i1 (operands[0], operands[3]);
++ rtx lab = function_symbol (operands[3], "__udivsi3", SFUNC_STATIC).lab;
++ last = gen_udivsi3_i1 (operands[0], operands[3], lab);
+ }
+ emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
+ emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
+@@ -2906,7 +2918,7 @@ (define_insn_and_split "*divsi_inv_call_combine"
+ emit_move_insn (gen_rtx_REG (DImode, R20_REG), x);
+ break;
+ }
+- sym = function_symbol (NULL, name, kind);
++ sym = function_symbol (NULL, name, kind).sym;
+ emit_insn (gen_divsi3_media_2 (operands[0], sym));
+ DONE;
+ }
+@@ -2926,31 +2938,37 @@ (define_expand "divsi3_i4_media"
+ })
+
+ (define_insn "divsi3_i4"
+- [(set (match_operand:SI 0 "register_operand" "=y")
++ [(set (match_operand:SI 0 "register_operand" "=y,y")
+ (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
+ (clobber (reg:SI PR_REG))
+ (clobber (reg:DF DR0_REG))
+ (clobber (reg:DF DR2_REG))
+ (clobber (reg:SI FPSCR_STAT_REG))
+- (use (match_operand:SI 1 "arith_reg_operand" "r"))
++ (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
++ (use (match_operand 2 "" "Z,Ccl"))
+ (use (reg:SI FPSCR_MODES_REG))]
+ "TARGET_FPU_DOUBLE && ! TARGET_FPU_SINGLE"
+- "jsr @%1%#"
++ "@
++ jsr @%1%#
++ bsrf %1\n%O2:%#"
+ [(set_attr "type" "sfunc")
+ (set_attr "fp_mode" "double")
+ (set_attr "needs_delay_slot" "yes")])
+
+ (define_insn "divsi3_i4_single"
+- [(set (match_operand:SI 0 "register_operand" "=y")
++ [(set (match_operand:SI 0 "register_operand" "=y,y")
+ (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
+ (clobber (reg:SI PR_REG))
+ (clobber (reg:DF DR0_REG))
+ (clobber (reg:DF DR2_REG))
+ (clobber (reg:SI R2_REG))
+- (use (match_operand:SI 1 "arith_reg_operand" "r"))]
++ (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
++ (use (match_operand 2 "" "Z,Ccl"))]
+ "(TARGET_FPU_SINGLE_ONLY || TARGET_FPU_DOUBLE || TARGET_SHCOMPACT)
+ && TARGET_FPU_SINGLE"
+- "jsr @%1%#"
++ "@
++ jsr @%1%#
++ bsrf %1\n%O2:%#"
+ [(set_attr "type" "sfunc")
+ (set_attr "needs_delay_slot" "yes")])
+
+@@ -2994,11 +3012,12 @@ (define_expand "divsi3"
+ }
+ else if (TARGET_DIVIDE_CALL_FP)
+ {
+- function_symbol (operands[3], sh_divsi3_libfunc, SFUNC_STATIC);
++ rtx lab = function_symbol (operands[3], sh_divsi3_libfunc,
++ SFUNC_STATIC).lab;
+ if (TARGET_FPU_SINGLE)
+- last = gen_divsi3_i4_single (operands[0], operands[3]);
++ last = gen_divsi3_i4_single (operands[0], operands[3], lab);
+ else
+- last = gen_divsi3_i4 (operands[0], operands[3]);
++ last = gen_divsi3_i4 (operands[0], operands[3], lab);
+ }
+ else if (TARGET_SH2A)
+ {
+@@ -3113,7 +3132,7 @@ (define_expand "divsi3"
+ last = ((TARGET_DIVIDE_CALL2 ? gen_divsi3_media_2 : gen_divsi3_i1_media)
+ (operands[0], operands[3]));
+ else if (TARGET_FPU_ANY)
+- last = gen_divsi3_i4_single (operands[0], operands[3]);
++ last = gen_divsi3_i4_single (operands[0], operands[3], const0_rtx);
+ else
+ last = gen_divsi3_i1 (operands[0], operands[3]);
+ }
+@@ -3713,7 +3732,7 @@ (define_expand "mulsi3"
+ {
+ /* The address must be set outside the libcall,
+ since it goes into a pseudo. */
+- rtx sym = function_symbol (NULL, "__mulsi3", SFUNC_STATIC);
++ rtx sym = function_symbol (NULL, "__mulsi3", SFUNC_STATIC).sym;
+ rtx addr = force_reg (SImode, sym);
+ rtx insns = gen_mulsi3_call (operands[0], operands[1],
+ operands[2], addr);
+@@ -4970,8 +4989,8 @@ (define_expand "ashlsi3"
+ {
+ emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
+ rtx funcaddr = gen_reg_rtx (Pmode);
+- function_symbol (funcaddr, "__ashlsi3_r0", SFUNC_STATIC);
+- emit_insn (gen_ashlsi3_d_call (operands[0], operands[2], funcaddr));
++ rtx lab = function_symbol (funcaddr, "__ashlsi3_r0", SFUNC_STATIC).lab;
++ emit_insn (gen_ashlsi3_d_call (operands[0], operands[2], funcaddr, lab));
+
+ DONE;
+ }
+@@ -5024,15 +5043,18 @@ (define_insn_and_split "ashlsi3_d"
+ ;; In order to make combine understand the truncation of the shift amount
+ ;; operand we have to allow it to use pseudo regs for the shift operands.
+ (define_insn "ashlsi3_d_call"
+- [(set (match_operand:SI 0 "arith_reg_dest" "=z")
++ [(set (match_operand:SI 0 "arith_reg_dest" "=z,z")
+ (ashift:SI (reg:SI R4_REG)
+- (and:SI (match_operand:SI 1 "arith_reg_operand" "z")
++ (and:SI (match_operand:SI 1 "arith_reg_operand" "z,z")
+ (const_int 31))))
+- (use (match_operand:SI 2 "arith_reg_operand" "r"))
++ (use (match_operand:SI 2 "arith_reg_operand" "r,r"))
++ (use (match_operand 3 "" "Z,Ccl"))
+ (clobber (reg:SI T_REG))
+ (clobber (reg:SI PR_REG))]
+ "TARGET_SH1 && !TARGET_DYNSHIFT"
+- "jsr @%2%#"
++ "@
++ jsr @%2%#
++ bsrf %2\n%O3:%#"
+ [(set_attr "type" "sfunc")
+ (set_attr "needs_delay_slot" "yes")])
+
+@@ -5374,12 +5396,15 @@ (define_insn "ashrsi3_d"
+ (define_insn "ashrsi3_n"
+ [(set (reg:SI R4_REG)
+ (ashiftrt:SI (reg:SI R4_REG)
+- (match_operand:SI 0 "const_int_operand" "i")))
++ (match_operand:SI 0 "const_int_operand" "i,i")))
+ (clobber (reg:SI T_REG))
+ (clobber (reg:SI PR_REG))
+- (use (match_operand:SI 1 "arith_reg_operand" "r"))]
++ (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
++ (use (match_operand 2 "" "Z,Ccl"))]
+ "TARGET_SH1"
+- "jsr @%1%#"
++ "@
++ jsr @%1%#
++ bsrf %1\n%O2:%#"
+ [(set_attr "type" "sfunc")
+ (set_attr "needs_delay_slot" "yes")])
+
+@@ -5532,8 +5557,8 @@ (define_expand "lshrsi3"
+ {
+ emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
+ rtx funcaddr = gen_reg_rtx (Pmode);
+- function_symbol (funcaddr, "__lshrsi3_r0", SFUNC_STATIC);
+- emit_insn (gen_lshrsi3_d_call (operands[0], operands[2], funcaddr));
++ rtx lab = function_symbol (funcaddr, "__lshrsi3_r0", SFUNC_STATIC).lab;
++ emit_insn (gen_lshrsi3_d_call (operands[0], operands[2], funcaddr, lab));
+ DONE;
+ }
+ })
+@@ -5585,15 +5610,18 @@ (define_insn_and_split "lshrsi3_d"
+ ;; In order to make combine understand the truncation of the shift amount
+ ;; operand we have to allow it to use pseudo regs for the shift operands.
+ (define_insn "lshrsi3_d_call"
+- [(set (match_operand:SI 0 "arith_reg_dest" "=z")
++ [(set (match_operand:SI 0 "arith_reg_dest" "=z,z")
+ (lshiftrt:SI (reg:SI R4_REG)
+- (and:SI (match_operand:SI 1 "arith_reg_operand" "z")
++ (and:SI (match_operand:SI 1 "arith_reg_operand" "z,z")
+ (const_int 31))))
+- (use (match_operand:SI 2 "arith_reg_operand" "r"))
++ (use (match_operand:SI 2 "arith_reg_operand" "r,r"))
++ (use (match_operand 3 "" "Z,Ccl"))
+ (clobber (reg:SI T_REG))
+ (clobber (reg:SI PR_REG))]
+ "TARGET_SH1 && !TARGET_DYNSHIFT"
+- "jsr @%2%#"
++ "@
++ jsr @%2%#
++ bsrf %2\n%O3:%#"
+ [(set_attr "type" "sfunc")
+ (set_attr "needs_delay_slot" "yes")])
+
+@@ -7315,7 +7343,7 @@ (define_expand "ic_invalidate_line"
+ }
+ else if (TARGET_SHCOMPACT)
+ {
+- operands[1] = function_symbol (NULL, "__ic_invalidate", SFUNC_STATIC);
++ operands[1] = function_symbol (NULL, "__ic_invalidate", SFUNC_STATIC).sym;
+ operands[1] = force_reg (Pmode, operands[1]);
+ emit_insn (gen_ic_invalidate_line_compact (operands[0], operands[1]));
+ DONE;
+@@ -7397,7 +7425,7 @@ (define_expand "initialize_trampoline"
+
+ tramp = force_reg (Pmode, operands[0]);
+ sfun = force_reg (Pmode, function_symbol (NULL, "__init_trampoline",
+- SFUNC_STATIC));
++ SFUNC_STATIC).sym);
+ emit_move_insn (gen_rtx_REG (SImode, R2_REG), operands[1]);
+ emit_move_insn (gen_rtx_REG (SImode, R3_REG), operands[2]);
+
+@@ -9459,9 +9487,29 @@ (define_insn "calli"
+ (match_operand 1 "" ""))
+ (use (reg:SI FPSCR_MODES_REG))
+ (clobber (reg:SI PR_REG))]
+- "TARGET_SH1"
++ "TARGET_SH1 && !TARGET_FDPIC"
+ {
+- if (TARGET_SH2A && (dbr_sequence_length () == 0))
++ if (TARGET_SH2A && dbr_sequence_length () == 0)
++ return "jsr/n @%0";
++ else
++ return "jsr @%0%#";
++}
++ [(set_attr "type" "call")
++ (set (attr "fp_mode")
++ (if_then_else (eq_attr "fpu_single" "yes")
++ (const_string "single") (const_string "double")))
++ (set_attr "needs_delay_slot" "yes")
++ (set_attr "fp_set" "unknown")])
++
++(define_insn "calli_fdpic"
++ [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
++ (match_operand 1))
++ (use (reg:SI FPSCR_MODES_REG))
++ (use (reg:SI PIC_REG))
++ (clobber (reg:SI PR_REG))]
++ "TARGET_FDPIC"
++{
++ if (TARGET_SH2A && dbr_sequence_length () == 0)
+ return "jsr/n @%0";
+ else
+ return "jsr @%0%#";
+@@ -9588,9 +9636,30 @@ (define_insn "call_valuei"
+ (match_operand 2 "" "")))
+ (use (reg:SI FPSCR_MODES_REG))
+ (clobber (reg:SI PR_REG))]
+- "TARGET_SH1"
++ "TARGET_SH1 && !TARGET_FDPIC"
++{
++ if (TARGET_SH2A && dbr_sequence_length () == 0)
++ return "jsr/n @%1";
++ else
++ return "jsr @%1%#";
++}
++ [(set_attr "type" "call")
++ (set (attr "fp_mode")
++ (if_then_else (eq_attr "fpu_single" "yes")
++ (const_string "single") (const_string "double")))
++ (set_attr "needs_delay_slot" "yes")
++ (set_attr "fp_set" "unknown")])
++
++(define_insn "call_valuei_fdpic"
++ [(set (match_operand 0 "" "=rf")
++ (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
++ (match_operand 2)))
++ (use (reg:SI FPSCR_REG))
++ (use (reg:SI PIC_REG))
++ (clobber (reg:SI PR_REG))]
++ "TARGET_FDPIC"
+ {
+- if (TARGET_SH2A && (dbr_sequence_length () == 0))
++ if (TARGET_SH2A && dbr_sequence_length () == 0)
+ return "jsr/n @%1";
+ else
+ return "jsr @%1%#";
+@@ -9725,6 +9794,12 @@ (define_expand "call"
+ (clobber (reg:SI PR_REG))])]
+ ""
+ {
++ if (TARGET_FDPIC)
++ {
++ rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
++ emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ());
++ }
++
+ if (TARGET_SHMEDIA)
+ {
+ operands[0] = shmedia_prepare_call_address (operands[0], 0);
+@@ -9759,8 +9834,8 @@ (define_expand "call"
+ run out of registers when adjusting fpscr for the call. */
+ emit_insn (gen_force_mode_for_call ());
+
+- operands[0]
+- = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT);
++ operands[0] = function_symbol (NULL, "__GCC_shcompact_call_trampoline",
++ SFUNC_GOT).sym;
+ operands[0] = force_reg (SImode, operands[0]);
+
+ emit_move_insn (r0, func);
+@@ -9808,7 +9883,13 @@ (define_expand "call"
+ operands[1] = operands[2];
+ }
+
+- emit_call_insn (gen_calli (operands[0], operands[1]));
++ if (TARGET_FDPIC)
++ {
++ operands[0] = sh_load_function_descriptor (operands[0]);
++ emit_call_insn (gen_calli_fdpic (operands[0], operands[1]));
++ }
++ else
++ emit_call_insn (gen_calli (operands[0], operands[1]));
+ DONE;
+ })
+
+@@ -9888,7 +9969,7 @@ (define_expand "call_pop"
+ emit_insn (gen_force_mode_for_call ());
+
+ operands[0] = function_symbol (NULL, "__GCC_shcompact_call_trampoline",
+- SFUNC_GOT);
++ SFUNC_GOT).sym;
+ operands[0] = force_reg (SImode, operands[0]);
+
+ emit_move_insn (r0, func);
+@@ -9913,6 +9994,12 @@ (define_expand "call_value"
+ (clobber (reg:SI PR_REG))])]
+ ""
+ {
++ if (TARGET_FDPIC)
++ {
++ rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
++ emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ());
++ }
++
+ if (TARGET_SHMEDIA)
+ {
+ operands[1] = shmedia_prepare_call_address (operands[1], 0);
+@@ -9948,8 +10035,8 @@ (define_expand "call_value"
+ run out of registers when adjusting fpscr for the call. */
+ emit_insn (gen_force_mode_for_call ());
+
+- operands[1]
+- = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT);
++ operands[1] = function_symbol (NULL, "__GCC_shcompact_call_trampoline",
++ SFUNC_GOT).sym;
+ operands[1] = force_reg (SImode, operands[1]);
+
+ emit_move_insn (r0, func);
+@@ -9997,7 +10084,14 @@ (define_expand "call_value"
+ else
+ operands[1] = force_reg (SImode, XEXP (operands[1], 0));
+
+- emit_call_insn (gen_call_valuei (operands[0], operands[1], operands[2]));
++ if (TARGET_FDPIC)
++ {
++ operands[1] = sh_load_function_descriptor (operands[1]);
++ emit_call_insn (gen_call_valuei_fdpic (operands[0], operands[1],
++ operands[2]));
++ }
++ else
++ emit_call_insn (gen_call_valuei (operands[0], operands[1], operands[2]));
+ DONE;
+ })
+
+@@ -10006,7 +10100,21 @@ (define_insn "sibcalli"
+ (match_operand 1 "" ""))
+ (use (reg:SI FPSCR_MODES_REG))
+ (return)]
+- "TARGET_SH1"
++ "TARGET_SH1 && !TARGET_FDPIC"
++ "jmp @%0%#"
++ [(set_attr "needs_delay_slot" "yes")
++ (set (attr "fp_mode")
++ (if_then_else (eq_attr "fpu_single" "yes")
++ (const_string "single") (const_string "double")))
++ (set_attr "type" "jump_ind")])
++
++(define_insn "sibcalli_fdpic"
++ [(call (mem:SI (match_operand:SI 0 "register_operand" "k"))
++ (match_operand 1))
++ (use (reg:SI FPSCR_MODES_REG))
++ (use (reg:SI PIC_REG))
++ (return)]
++ "TARGET_FDPIC"
+ "jmp @%0%#"
+ [(set_attr "needs_delay_slot" "yes")
+ (set (attr "fp_mode")
+@@ -10020,7 +10128,25 @@ (define_insn "sibcalli_pcrel"
+ (use (match_operand 2 "" ""))
+ (use (reg:SI FPSCR_MODES_REG))
+ (return)]
+- "TARGET_SH2"
++ "TARGET_SH2 && !TARGET_FDPIC"
++{
++ return "braf %0" "\n"
++ "%O2:%#";
++}
++ [(set_attr "needs_delay_slot" "yes")
++ (set (attr "fp_mode")
++ (if_then_else (eq_attr "fpu_single" "yes")
++ (const_string "single") (const_string "double")))
++ (set_attr "type" "jump_ind")])
++
++(define_insn "sibcalli_pcrel_fdpic"
++ [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "k"))
++ (match_operand 1))
++ (use (match_operand 2))
++ (use (reg:SI FPSCR_MODES_REG))
++ (use (reg:SI PIC_REG))
++ (return)]
++ "TARGET_SH2 && TARGET_FDPIC"
+ {
+ return "braf %0" "\n"
+ "%O2:%#";
+@@ -10053,7 +10179,7 @@ (define_insn_and_split "sibcall_pcrel"
+ (use (reg:SI FPSCR_MODES_REG))
+ (clobber (match_scratch:SI 2 "=&k"))
+ (return)]
+- "TARGET_SH2"
++ "TARGET_SH2 && !TARGET_FDPIC"
+ "#"
+ "reload_completed"
+ [(const_int 0)]
+@@ -10073,6 +10199,32 @@ (define_insn_and_split "sibcall_pcrel"
+ (const_string "single") (const_string "double")))
+ (set_attr "type" "jump_ind")])
+
++(define_insn_and_split "sibcall_pcrel_fdpic"
++ [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand"))
++ (match_operand 1))
++ (use (reg:SI FPSCR_MODES_REG))
++ (use (reg:SI PIC_REG))
++ (clobber (match_scratch:SI 2 "=k"))
++ (return)]
++ "TARGET_SH2 && TARGET_FDPIC"
++ "#"
++ "&& reload_completed"
++ [(const_int 0)]
++{
++ rtx lab = PATTERN (gen_call_site ());
++
++ sh_expand_sym_label2reg (operands[2], operands[0], lab, true);
++ rtx i = emit_call_insn (gen_sibcalli_pcrel_fdpic (operands[2], operands[1],
++ copy_rtx (lab)));
++ SIBLING_CALL_P (i) = 1;
++ DONE;
++}
++ [(set_attr "needs_delay_slot" "yes")
++ (set (attr "fp_mode")
++ (if_then_else (eq_attr "fpu_single" "yes")
++ (const_string "single") (const_string "double")))
++ (set_attr "type" "jump_ind")])
++
+ (define_insn "sibcall_compact"
+ [(call (mem:SI (match_operand:SI 0 "register_operand" "k,k"))
+ (match_operand 1 "" ""))
+@@ -10117,6 +10269,12 @@ (define_expand "sibcall"
+ (return)])]
+ ""
+ {
++ if (TARGET_FDPIC)
++ {
++ rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
++ emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ());
++ }
++
+ if (TARGET_SHMEDIA)
+ {
+ operands[0] = shmedia_prepare_call_address (operands[0], 1);
+@@ -10161,8 +10319,8 @@ (define_expand "sibcall"
+ run out of registers when adjusting fpscr for the call. */
+ emit_insn (gen_force_mode_for_call ());
+
+- operands[0]
+- = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT);
++ operands[0] = function_symbol (NULL, "__GCC_shcompact_call_trampoline",
++ SFUNC_GOT).sym;
+ operands[0] = force_reg (SImode, operands[0]);
+
+ /* We don't need a return trampoline, since the callee will
+@@ -10196,13 +10354,23 @@ (define_expand "sibcall"
+ static functions. */
+ && SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
+ {
+- emit_call_insn (gen_sibcall_pcrel (XEXP (operands[0], 0), operands[1]));
++ if (TARGET_FDPIC)
++ emit_call_insn (gen_sibcall_pcrel_fdpic (XEXP (operands[0], 0),
++ operands[1]));
++ else
++ emit_call_insn (gen_sibcall_pcrel (XEXP (operands[0], 0), operands[1]));
+ DONE;
+ }
+ else
+ operands[0] = force_reg (SImode, XEXP (operands[0], 0));
+
+- emit_call_insn (gen_sibcalli (operands[0], operands[1]));
++ if (TARGET_FDPIC)
++ {
++ operands[0] = sh_load_function_descriptor (operands[0]);
++ emit_call_insn (gen_sibcalli_fdpic (operands[0], operands[1]));
++ }
++ else
++ emit_call_insn (gen_sibcalli (operands[0], operands[1]));
+ DONE;
+ })
+
+@@ -10212,7 +10380,22 @@ (define_insn "sibcall_valuei"
+ (match_operand 2 "" "")))
+ (use (reg:SI FPSCR_MODES_REG))
+ (return)]
+- "TARGET_SH1"
++ "TARGET_SH1 && !TARGET_FDPIC"
++ "jmp @%1%#"
++ [(set_attr "needs_delay_slot" "yes")
++ (set (attr "fp_mode")
++ (if_then_else (eq_attr "fpu_single" "yes")
++ (const_string "single") (const_string "double")))
++ (set_attr "type" "jump_ind")])
++
++(define_insn "sibcall_valuei_fdpic"
++ [(set (match_operand 0 "" "=rf")
++ (call (mem:SI (match_operand:SI 1 "register_operand" "k"))
++ (match_operand 2)))
++ (use (reg:SI FPSCR_MODES_REG))
++ (use (reg:SI PIC_REG))
++ (return)]
++ "TARGET_FDPIC"
+ "jmp @%1%#"
+ [(set_attr "needs_delay_slot" "yes")
+ (set (attr "fp_mode")
+@@ -10227,7 +10410,26 @@ (define_insn "sibcall_valuei_pcrel"
+ (use (match_operand 3 "" ""))
+ (use (reg:SI FPSCR_MODES_REG))
+ (return)]
+- "TARGET_SH2"
++ "TARGET_SH2 && !TARGET_FDPIC"
++{
++ return "braf %1" "\n"
++ "%O3:%#";
++}
++ [(set_attr "needs_delay_slot" "yes")
++ (set (attr "fp_mode")
++ (if_then_else (eq_attr "fpu_single" "yes")
++ (const_string "single") (const_string "double")))
++ (set_attr "type" "jump_ind")])
++
++(define_insn "sibcall_valuei_pcrel_fdpic"
++ [(set (match_operand 0 "" "=rf")
++ (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "k"))
++ (match_operand 2)))
++ (use (match_operand 3))
++ (use (reg:SI FPSCR_MODES_REG))
++ (use (reg:SI PIC_REG))
++ (return)]
++ "TARGET_SH2 && TARGET_FDPIC"
+ {
+ return "braf %1" "\n"
+ "%O3:%#";
+@@ -10245,7 +10447,7 @@ (define_insn_and_split "sibcall_value_pcrel"
+ (use (reg:SI FPSCR_MODES_REG))
+ (clobber (match_scratch:SI 3 "=&k"))
+ (return)]
+- "TARGET_SH2"
++ "TARGET_SH2 && !TARGET_FDPIC"
+ "#"
+ "reload_completed"
+ [(const_int 0)]
+@@ -10267,6 +10469,35 @@ (define_insn_and_split "sibcall_value_pcrel"
+ (const_string "single") (const_string "double")))
+ (set_attr "type" "jump_ind")])
+
++(define_insn_and_split "sibcall_value_pcrel_fdpic"
++ [(set (match_operand 0 "" "=rf")
++ (call (mem:SI (match_operand:SI 1 "symbol_ref_operand"))
++ (match_operand 2)))
++ (use (reg:SI FPSCR_MODES_REG))
++ (use (reg:SI PIC_REG))
++ (clobber (match_scratch:SI 3 "=k"))
++ (return)]
++ "TARGET_SH2 && TARGET_FDPIC"
++ "#"
++ "&& reload_completed"
++ [(const_int 0)]
++{
++ rtx lab = PATTERN (gen_call_site ());
++
++ sh_expand_sym_label2reg (operands[3], operands[1], lab, true);
++ rtx i = emit_call_insn (gen_sibcall_valuei_pcrel_fdpic (operands[0],
++ operands[3],
++ operands[2],
++ copy_rtx (lab)));
++ SIBLING_CALL_P (i) = 1;
++ DONE;
++}
++ [(set_attr "needs_delay_slot" "yes")
++ (set (attr "fp_mode")
++ (if_then_else (eq_attr "fpu_single" "yes")
++ (const_string "single") (const_string "double")))
++ (set_attr "type" "jump_ind")])
++
+ (define_insn "sibcall_value_compact"
+ [(set (match_operand 0 "" "=rf,rf")
+ (call (mem:SI (match_operand:SI 1 "register_operand" "k,k"))
+@@ -10314,6 +10545,12 @@ (define_expand "sibcall_value"
+ (return)])]
+ ""
+ {
++ if (TARGET_FDPIC)
++ {
++ rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
++ emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ());
++ }
++
+ if (TARGET_SHMEDIA)
+ {
+ operands[1] = shmedia_prepare_call_address (operands[1], 1);
+@@ -10359,8 +10596,8 @@ (define_expand "sibcall_value"
+ run out of registers when adjusting fpscr for the call. */
+ emit_insn (gen_force_mode_for_call ());
+
+- operands[1]
+- = function_symbol (NULL, "__GCC_shcompact_call_trampoline", SFUNC_GOT);
++ operands[1] = function_symbol (NULL, "__GCC_shcompact_call_trampoline",
++ SFUNC_GOT).sym;
+ operands[1] = force_reg (SImode, operands[1]);
+
+ /* We don't need a return trampoline, since the callee will
+@@ -10395,15 +10632,27 @@ (define_expand "sibcall_value"
+ static functions. */
+ && SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0)))
+ {
+- emit_call_insn (gen_sibcall_value_pcrel (operands[0],
+- XEXP (operands[1], 0),
+- operands[2]));
++ if (TARGET_FDPIC)
++ emit_call_insn (gen_sibcall_value_pcrel_fdpic (operands[0],
++ XEXP (operands[1], 0),
++ operands[2]));
++ else
++ emit_call_insn (gen_sibcall_value_pcrel (operands[0],
++ XEXP (operands[1], 0),
++ operands[2]));
+ DONE;
+ }
+ else
+ operands[1] = force_reg (SImode, XEXP (operands[1], 0));
+
+- emit_call_insn (gen_sibcall_valuei (operands[0], operands[1], operands[2]));
++ if (TARGET_FDPIC)
++ {
++ operands[1] = sh_load_function_descriptor (operands[1]);
++ emit_call_insn (gen_sibcall_valuei_fdpic (operands[0], operands[1],
++ operands[2]));
++ }
++ else
++ emit_call_insn (gen_sibcall_valuei (operands[0], operands[1], operands[2]));
+ DONE;
+ })
+
+@@ -10487,7 +10736,7 @@ (define_expand "call_value_pop"
+ emit_insn (gen_force_mode_for_call ());
+
+ operands[1] = function_symbol (NULL, "__GCC_shcompact_call_trampoline",
+- SFUNC_GOT);
++ SFUNC_GOT).sym;
+ operands[1] = force_reg (SImode, operands[1]);
+
+ emit_move_insn (r0, func);
+@@ -10685,6 +10934,13 @@ (define_expand "GOTaddr2picreg"
+ DONE;
+ }
+
++ if (TARGET_FDPIC)
++ {
++ rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
++ emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ());
++ DONE;
++ }
++
+ operands[1] = gen_rtx_REG (Pmode, PIC_REG);
+ operands[2] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
+
+@@ -10820,10 +11076,13 @@ (define_expand "symGOT_load"
+ rtx mem;
+ bool stack_chk_guard_p = false;
+
++ rtx picreg = TARGET_FDPIC ? sh_get_fdpic_reg_initial_val ()
++ : gen_rtx_REG (Pmode, PIC_REG);
++
+ operands[2] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
+ operands[3] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
+
+- if (!TARGET_SHMEDIA
++ if (!TARGET_SHMEDIA && !TARGET_FDPIC
+ && flag_stack_protect
+ && GET_CODE (operands[1]) == CONST
+ && GET_CODE (XEXP (operands[1], 0)) == UNSPEC
+@@ -10862,8 +11121,7 @@ (define_expand "symGOT_load"
+ if (stack_chk_guard_p)
+ emit_insn (gen_chk_guard_add (operands[3], operands[2]));
+ else
+- emit_move_insn (operands[3], gen_rtx_PLUS (Pmode, operands[2],
+- gen_rtx_REG (Pmode, PIC_REG)));
++ emit_move_insn (operands[3], gen_rtx_PLUS (Pmode, operands[2], picreg));
+
+ /* N.B. This is not constant for a GOTPLT relocation. */
+ mem = gen_rtx_MEM (Pmode, operands[3]);
+@@ -10894,6 +11152,23 @@ (define_expand "symGOT2reg"
+ DONE;
+ })
+
++(define_expand "sym2GOTFUNCDESC"
++ [(const (unspec [(match_operand 0)] UNSPEC_GOTFUNCDESC))]
++ "TARGET_FDPIC")
++
++(define_expand "symGOTFUNCDESC2reg"
++ [(match_operand 0) (match_operand 1)]
++ "TARGET_FDPIC"
++{
++ rtx gotsym = gen_sym2GOTFUNCDESC (operands[1]);
++ PUT_MODE (gotsym, Pmode);
++ rtx insn = emit_insn (gen_symGOT_load (operands[0], gotsym));
++
++ MEM_READONLY_P (SET_SRC (PATTERN (insn))) = 1;
++
++ DONE;
++})
++
+ (define_expand "symGOTPLT2reg"
+ [(match_operand 0 "" "") (match_operand 1 "" "")]
+ ""
+@@ -10920,18 +11195,39 @@ (define_expand "symGOTOFF2reg"
+ ? operands[0]
+ : gen_reg_rtx (GET_MODE (operands[0])));
+
++ rtx picreg = TARGET_FDPIC ? sh_get_fdpic_reg_initial_val ()
++ : gen_rtx_REG (Pmode, PIC_REG);
++
+ gotoffsym = gen_sym2GOTOFF (operands[1]);
+ PUT_MODE (gotoffsym, Pmode);
+ emit_move_insn (t, gotoffsym);
+- insn = emit_move_insn (operands[0],
+- gen_rtx_PLUS (Pmode, t,
+- gen_rtx_REG (Pmode, PIC_REG)));
++ insn = emit_move_insn (operands[0], gen_rtx_PLUS (Pmode, t, picreg));
+
+ set_unique_reg_note (insn, REG_EQUAL, operands[1]);
+
+ DONE;
+ })
+
++(define_expand "sym2GOTOFFFUNCDESC"
++ [(const (unspec [(match_operand 0)] UNSPEC_GOTOFFFUNCDESC))]
++ "TARGET_FDPIC")
++
++(define_expand "symGOTOFFFUNCDESC2reg"
++ [(match_operand 0) (match_operand 1)]
++ "TARGET_FDPIC"
++{
++ rtx picreg = sh_get_fdpic_reg_initial_val ();
++ rtx t = !can_create_pseudo_p ()
++ ? operands[0]
++ : gen_reg_rtx (GET_MODE (operands[0]));
++
++ rtx gotoffsym = gen_sym2GOTOFFFUNCDESC (operands[1]);
++ PUT_MODE (gotoffsym, Pmode);
++ emit_move_insn (t, gotoffsym);
++ emit_move_insn (operands[0], gen_rtx_PLUS (Pmode, t, picreg));
++ DONE;
++})
++
+ (define_expand "symPLT_label2reg"
+ [(set (match_operand:SI 0 "" "")
+ (const:SI
+@@ -12688,18 +12984,22 @@ (define_expand "movmemsi"
+ (define_insn "block_move_real"
+ [(parallel [(set (mem:BLK (reg:SI R4_REG))
+ (mem:BLK (reg:SI R5_REG)))
+- (use (match_operand:SI 0 "arith_reg_operand" "r"))
++ (use (match_operand:SI 0 "arith_reg_operand" "r,r"))
++ (use (match_operand 1 "" "Z,Ccl"))
+ (clobber (reg:SI PR_REG))
+ (clobber (reg:SI R0_REG))])]
+ "TARGET_SH1 && ! TARGET_HARD_SH4"
+- "jsr @%0%#"
++ "@
++ jsr @%0%#
++ bsrf %0\n%O1:%#"
+ [(set_attr "type" "sfunc")
+ (set_attr "needs_delay_slot" "yes")])
+
+ (define_insn "block_lump_real"
+ [(parallel [(set (mem:BLK (reg:SI R4_REG))
+ (mem:BLK (reg:SI R5_REG)))
+- (use (match_operand:SI 0 "arith_reg_operand" "r"))
++ (use (match_operand:SI 0 "arith_reg_operand" "r,r"))
++ (use (match_operand 1 "" "Z,Ccl"))
+ (use (reg:SI R6_REG))
+ (clobber (reg:SI PR_REG))
+ (clobber (reg:SI T_REG))
+@@ -12708,27 +13008,33 @@ (define_insn "block_lump_real"
+ (clobber (reg:SI R6_REG))
+ (clobber (reg:SI R0_REG))])]
+ "TARGET_SH1 && ! TARGET_HARD_SH4"
+- "jsr @%0%#"
++ "@
++ jsr @%0%#
++ bsrf %0\n%O1:%#"
+ [(set_attr "type" "sfunc")
+ (set_attr "needs_delay_slot" "yes")])
+
+ (define_insn "block_move_real_i4"
+ [(parallel [(set (mem:BLK (reg:SI R4_REG))
+ (mem:BLK (reg:SI R5_REG)))
+- (use (match_operand:SI 0 "arith_reg_operand" "r"))
++ (use (match_operand:SI 0 "arith_reg_operand" "r,r"))
++ (use (match_operand 1 "" "Z,Ccl"))
+ (clobber (reg:SI PR_REG))
+ (clobber (reg:SI R0_REG))
+ (clobber (reg:SI R1_REG))
+ (clobber (reg:SI R2_REG))])]
+ "TARGET_HARD_SH4"
+- "jsr @%0%#"
++ "@
++ jsr @%0%#
++ bsrf %0\n%O1:%#"
+ [(set_attr "type" "sfunc")
+ (set_attr "needs_delay_slot" "yes")])
+
+ (define_insn "block_lump_real_i4"
+ [(parallel [(set (mem:BLK (reg:SI R4_REG))
+ (mem:BLK (reg:SI R5_REG)))
+- (use (match_operand:SI 0 "arith_reg_operand" "r"))
++ (use (match_operand:SI 0 "arith_reg_operand" "r,r"))
++ (use (match_operand 1 "" "Z,Ccl"))
+ (use (reg:SI R6_REG))
+ (clobber (reg:SI PR_REG))
+ (clobber (reg:SI T_REG))
+@@ -12740,7 +13046,9 @@ (define_insn "block_lump_real_i4"
+ (clobber (reg:SI R2_REG))
+ (clobber (reg:SI R3_REG))])]
+ "TARGET_HARD_SH4"
+- "jsr @%0%#"
++ "@
++ jsr @%0%#
++ bsrf %0\n%O1:%#"
+ [(set_attr "type" "sfunc")
+ (set_attr "needs_delay_slot" "yes")])
+
+diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt
+index 8875b5d..c2e8aca 100644
+--- a/gcc/config/sh/sh.opt
++++ b/gcc/config/sh/sh.opt
+@@ -264,6 +264,10 @@ mdivsi3_libfunc=
+ Target RejectNegative Joined Var(sh_divsi3_libfunc) Init("")
+ Specify name for 32 bit signed division function
+
++mfdpic
++Target Report Var(TARGET_FDPIC) Init(0)
++Generate ELF FDPIC code
++
+ mfmovd
+ Target RejectNegative Mask(FMOVD)
+ Enable the use of 64-bit floating point registers in fmov instructions. See -mdalign if 64-bit alignment is required.
+diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi
+index 1fd773e..fe57b97 100644
+--- a/gcc/doc/install.texi
++++ b/gcc/doc/install.texi
+@@ -1810,6 +1810,9 @@ When neither of these configure options are used, the default will be
+ 128-bit @code{long double} when built against GNU C Library 2.4 and later,
+ 64-bit @code{long double} otherwise.
+
++@item --enable-fdpic
++On SH Linux systems, generate ELF FDPIC code.
++
+ @item --with-gmp=@var{pathname}
+ @itemx --with-gmp-include=@var{pathname}
+ @itemx --with-gmp-lib=@var{pathname}
+diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
+index ebfaaa1..8b26eac 100644
+--- a/gcc/doc/invoke.texi
++++ b/gcc/doc/invoke.texi
+@@ -21178,6 +21178,10 @@ in effect.
+ Prefer zero-displacement conditional branches for conditional move instruction
+ patterns. This can result in faster code on the SH4 processor.
+
++@item -mfdpic
++@opindex fdpic
++Generate code using the FDPIC ABI.
++
+ @end table
+
+ @node Solaris 2 Options
+diff --git a/include/longlong.h b/include/longlong.h
+index a0b2ce1..d7ef671 100644
+--- a/include/longlong.h
++++ b/include/longlong.h
+@@ -1102,6 +1102,33 @@ extern UDItype __umulsidi3 (USItype, USItype);
+ /* This is the same algorithm as __udiv_qrnnd_c. */
+ #define UDIV_NEEDS_NORMALIZATION 1
+
++#ifdef __FDPIC__
++/* FDPIC needs a special version of the asm fragment to extract the
++ code address from the function descriptor. __udiv_qrnnd_16 is
++ assumed to be local and not to use the GOT, so loading r12 is
++ not needed. */
++#define udiv_qrnnd(q, r, n1, n0, d) \
++ do { \
++ extern UWtype __udiv_qrnnd_16 (UWtype, UWtype) \
++ __attribute__ ((visibility ("hidden"))); \
++ /* r0: rn r1: qn */ /* r0: n1 r4: n0 r5: d r6: d1 */ /* r2: __m */ \
++ __asm__ ( \
++ "mov%M4 %4,r5\n" \
++" swap.w %3,r4\n" \
++" swap.w r5,r6\n" \
++" mov.l @%5,r2\n" \
++" jsr @r2\n" \
++" shll16 r6\n" \
++" swap.w r4,r4\n" \
++" mov.l @%5,r2\n" \
++" jsr @r2\n" \
++" swap.w r1,%0\n" \
++" or r1,%0" \
++ : "=r" (q), "=&z" (r) \
++ : "1" (n1), "r" (n0), "rm" (d), "r" (&__udiv_qrnnd_16) \
++ : "r1", "r2", "r4", "r5", "r6", "pr", "t"); \
++ } while (0)
++#else
+ #define udiv_qrnnd(q, r, n1, n0, d) \
+ do { \
+ extern UWtype __udiv_qrnnd_16 (UWtype, UWtype) \
+@@ -1121,6 +1148,7 @@ extern UDItype __umulsidi3 (USItype, USItype);
+ : "1" (n1), "r" (n0), "rm" (d), "r" (&__udiv_qrnnd_16) \
+ : "r1", "r2", "r4", "r5", "r6", "pr", "t"); \
+ } while (0)
++#endif /* __FDPIC__ */
+
+ #define UDIV_TIME 80
+
+diff --git a/libitm/config/sh/sjlj.S b/libitm/config/sh/sjlj.S
+index 410cef6..8c83fce 100644
+--- a/libitm/config/sh/sjlj.S
++++ b/libitm/config/sh/sjlj.S
+@@ -58,9 +58,6 @@ _ITM_beginTransaction:
+ jsr @r1
+ mov r15, r5
+ #else
+- mova .Lgot, r0
+- mov.l .Lgot, r12
+- add r0, r12
+ mov.l .Lbegin, r1
+ bsrf r1
+ mov r15, r5
+@@ -79,14 +76,12 @@ _ITM_beginTransaction:
+ nop
+ cfi_endproc
+
+- .align 2
+-.Lgot:
+- .long _GLOBAL_OFFSET_TABLE_
++ .align 2
+ .Lbegin:
+ #if defined HAVE_ATTRIBUTE_VISIBILITY || !defined __PIC__
+ .long GTM_begin_transaction
+ #else
+- .long GTM_begin_transaction@PLT-(.Lbegin0-.)
++ .long GTM_begin_transaction@PCREL-(.Lbegin0-.)
+ #endif
+ .size _ITM_beginTransaction, . - _ITM_beginTransaction
+
--- /dev/null
+--- a/gcc/config/sh/sh.md (revision 233324)
++++ b/gcc/config/sh/sh.md (working copy)
+@@ -10476,7 +10476,7 @@
+ (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
+ (match_operand 2 "" "")))
+ (use (reg:SI FPSCR_MODES_REG))
+- (clobber (match_scratch:SI 3 "=&k"))
++ (clobber (reg:SI R1_REG))
+ (return)]
+ "TARGET_SH2 && !TARGET_FDPIC"
+ "#"
+@@ -10491,6 +10495,8 @@
+ rtx lab = PATTERN (gen_call_site ());
+ rtx call_insn;
+
++ operands[3] = gen_rtx_REG (SImode, R1_REG);
++
+ sh_expand_sym_label2reg (operands[3], operands[1], lab, true);
+ call_insn = emit_call_insn (gen_sibcall_valuei_pcrel (operands[0],
+ operands[3],
+@@ -10511,7 +10519,7 @@
+ (match_operand 2)))
+ (use (reg:SI FPSCR_MODES_REG))
+ (use (reg:SI PIC_REG))
+- (clobber (match_scratch:SI 3 "=k"))
++ (clobber (reg:SI R1_REG))
+ (return)]
+ "TARGET_SH2 && TARGET_FDPIC"
+ "#"
+@@ -10520,6 +10528,8 @@
+ {
+ rtx lab = PATTERN (gen_call_site ());
+
++ operands[3] = gen_rtx_REG (SImode, R1_REG);
++
+ sh_expand_sym_label2reg (operands[3], operands[1], lab, true);
+ rtx i = emit_call_insn (gen_sibcall_valuei_pcrel_fdpic (operands[0],
+ operands[3],
+
--- /dev/null
+--- a/libgcc/config/mips/linux-unwind.h 2016-04-07 23:08:58.088577977 +0000
++++ b/libgcc/config/mips/linux-unwind.h 2016-04-07 23:04:34.016523639 +0000
+@@ -27,7 +27,7 @@
+ state data appropriately. See unwind-dw2.c for the structs. */
+
+ #include <signal.h>
+-#include <asm/unistd.h>
++#include <sys/syscall.h>
+
+ /* The third parameter to the signal handler points to something with
+ * this structure defined in asm/ucontext.h, but the name clashes with
--- /dev/null
+diff -u a/Makefile b/Makefile
+--- a/Makefile 2016-05-11 10:23:26.000000000 +0100
++++ b/Makefile 2016-05-20 16:26:20.000000000 +0100
+@@ -1047,7 +1047,7 @@
+ archscripts:
+
+ PHONY += __headers
+-__headers: $(version_h) scripts_basic asm-generic archheaders archscripts FORCE
++__headers: $(version_h) scripts_basic asm-generic archheaders FORCE
+ $(Q)$(MAKE) $(build)=scripts build_unifdef
+
+ PHONY += headers_install_all
--- /dev/null
+TARGET = sh2eb-linux-muslfdpic
+GCC_CONFIG += --with-cpu=mj2
+
+# Optional to produce a smaller toolchain:
+# COMMON_CONFIG += --disable-nls
+# GCC_CONFIG += --disable-libquadmath --disable-decimal-float
--- /dev/null
+TARGET = sh2eb-linux-musl
+GCC_CONFIG += --with-cpu=mj2
+GCC_CONFIG += --enable-default-pie
+
+# This configuration should be compatible with the old GPLv2 tools,
+# but it is not regularly tested. Uncomment the following and remove
+# the above --with-cpu=mj2 in order to try:
+# GCC_VER = 4.2.1
+# BINUTILS_VER = 397a64b3
+# BINUTILS_SITE = http://landley.net/aboriginal/mirror
+
+# Optional to produce a smaller toolchain:
+# COMMON_CONFIG += --disable-nls
+# GCC_CONFIG += --disable-libquadmath --disable-decimal-float
--- /dev/null
+#
+# config.mak.dist - sample musl-cross-make configuration
+#
+# Copy to config.mak and edit as desired.
+#
+
+# There is no default TARGET; you must select one here or on the make
+# command line. Some examples:
+
+# TARGET = i486-linux-musl
+TARGET = x86_64-linux-musl
+# TARGET = arm-linux-musleabi
+# TARGET = arm-linux-musleabihf
+# TARGET = sh2eb-linux-muslfdpic
+# ...
+
+# By default, cross compilers are installed to ./output under the top-level
+# musl-cross-make directory and can later be moved wherever you want them.
+# To install directly to a specific location, set it here. Multiple targets
+# can safely be installed in the same location. Some examples:
+
+OUTPUT = $(PWD)/stage1
+
+# By default, latest supported release versions of musl and the toolchain
+# components are used. You can override those here, but the version selected
+# must be supported (under hashes/ and patches/) to work. For musl, you
+# can use "git-refname" (e.g. git-master) instead of a release. Setting a
+# blank version for gmp, mpc, mpfr and isl will suppress download and
+# in-tree build of these libraries and instead depend on pre-installed
+# libraries when available (isl is optional and not set by default).
+# Setting a blank version for linux will suppress installation of kernel
+# headers, which are not needed unless compiling programs that use them.
+
+# BINUTILS_VER = 2.25.1
+# GCC_VER = 5.2.0
+# MUSL_VER = git-master
+# GMP_VER =
+# MPC_VER =
+# MPFR_VER =
+# ISL_VER =
+# LINUX_VER =
+
+# Something like the following can be used to produce a static-linked
+# toolchain that's deployable to any system with matching arch, using
+# an existing musl-targeted cross compiler. This only # works if the
+# system you build on can natively (or via binfmt_misc and # qemu) run
+# binaries produced by the existing toolchain (in this example, i486).
+
+#COMMON_CONFIG += CC="x86_64-linux-musl-gcc -static --static" CXX="x86_64-linux-musl-g++ -static --static"
+
+# Recommended options for smaller build for deploying binaries:
+
+COMMON_CONFIG += CFLAGS="-g0 -Os" CXXFLAGS="-g0 -Os" LDFLAGS="-s"
+
+# Recommended options for faster/simpler build:
+
+COMMON_CONFIG += --disable-nls
+GCC_CONFIG += --enable-languages=c,c++
+GCC_CONFIG += --disable-libquadmath --disable-decimal-float
+GCC_CONFIG += --disable-multilib
+
+# You can keep the local build path out of your toolchain binaries and
+# target libraries with the following, but then gdb needs to be told
+# where to look for source files.
+
+# COMMON_CONFIG += --with-debug-prefix-map=$(PWD)=
--- /dev/null
+#
+# config.mak.dist - sample musl-cross-make configuration
+#
+# Copy to config.mak and edit as desired.
+#
+
+# There is no default TARGET; you must select one here or on the make
+# command line. Some examples:
+
+# TARGET = i486-linux-musl
+TARGET = x86_64-linux-musl
+# TARGET = arm-linux-musleabi
+# TARGET = arm-linux-musleabihf
+# TARGET = sh2eb-linux-muslfdpic
+# ...
+
+# By default, cross compilers are installed to ./output under the top-level
+# musl-cross-make directory and can later be moved wherever you want them.
+# To install directly to a specific location, set it here. Multiple targets
+# can safely be installed in the same location. Some examples:
+
+OUTPUT = $(PWD)/stage2
+
+# By default, latest supported release versions of musl and the toolchain
+# components are used. You can override those here, but the version selected
+# must be supported (under hashes/ and patches/) to work. For musl, you
+# can use "git-refname" (e.g. git-master) instead of a release. Setting a
+# blank version for gmp, mpc, mpfr and isl will suppress download and
+# in-tree build of these libraries and instead depend on pre-installed
+# libraries when available (isl is optional and not set by default).
+# Setting a blank version for linux will suppress installation of kernel
+# headers, which are not needed unless compiling programs that use them.
+
+# BINUTILS_VER = 2.25.1
+# GCC_VER = 5.2.0
+# MUSL_VER = git-master
+# GMP_VER =
+# MPC_VER =
+# MPFR_VER =
+# ISL_VER =
+# LINUX_VER =
+
+# Something like the following can be used to produce a static-linked
+# toolchain that's deployable to any system with matching arch, using
+# an existing musl-targeted cross compiler. This only # works if the
+# system you build on can natively (or via binfmt_misc and # qemu) run
+# binaries produced by the existing toolchain (in this example, i486).
+
+COMMON_CONFIG += CC="x86_64-linux-musl-gcc -static --static" CXX="x86_64-linux-musl-g++ -static --static"
+
+# Recommended options for smaller build for deploying binaries:
+
+COMMON_CONFIG += CFLAGS="-g0 -Os" CXXFLAGS="-g0 -Os" LDFLAGS="-s"
+
+# Recommended options for faster/simpler build:
+
+COMMON_CONFIG += --disable-nls
+GCC_CONFIG += --enable-languages=c,c++
+GCC_CONFIG += --disable-libquadmath --disable-decimal-float
+GCC_CONFIG += --disable-multilib
+
+# You can keep the local build path out of your toolchain binaries and
+# target libraries with the following, but then gdb needs to be told
+# where to look for source files.
+
+# COMMON_CONFIG += --with-debug-prefix-map=$(PWD)=
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